High speed and low power FPGA implementation of FIR filter for DSP applications

European Journal of Scientific Research

Volumn 31, Issue 1, 2009, Pages 19-28

  Shanthala, S ^a,b   Kulkarni, S Y ^b  

^a BANGALORE INSTITUTE OF TECHNOLOGY   (India)

^b NMAM INSTITUTE OF TECHNOLOGY   (India)

Author keywords

DSP; FIR filter; FPGA; Low power

Indexed keywords

EID: 67649810189     PISSN: 1450216X     EISSN: 1450202X     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

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2. U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays Second Edition, Springer, p.110.
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4. Wonyong Sung and Ki-Il Kum, 1995, "Simulation-Based Word-Length Optimization Method for Fixed-point Digital Signal Processing Systems", IEEE Transactions on Signal Processing, Vol. 43, No.12, December 1995.
5. X. Hu, L. S. DeBrunner, and V. DeBrunner, 2002, "An efficient design for FIR filters with Variable precision", Proc. 2002 IEEE Int. Symp. on Circuits and Systems, pp.365-368, vol. 4,May 2002.
6. Y. C. Lim, R. Yang, D. Li, and J. Song, 1999. "Signed-power-of-two term allocation scheme for the design of digital filters," IEEE Transactions on Circuits and Systems II, vol. 46, pp.577-584, May 1999.
7. S. C. Chan, W. Liu, and K. L. Ho, 2001, "Multiplier less perfect reconstruction modulated filterbanks with sum-of-powers-of-two coefficients," IEEE Signal Processing Letters, vol. 8, no. 6,pp. 163-166, June 2001.