Synthesizable high level hardware descriptions: Using statically typed two-level languages to guarantee Verilog synthesizability

Proceedings of the ACM SIGPLAN Symposium on Partial Evaluation and Semantics-Based Program Manipulation

Volumn , Issue , 2008, Pages 41-50

  Gillenwater, Jennifer ^a   Malecha, Gregory ^a   Salama, Cherif ^a   Zhu, Angela Yun ^a   Taha, Walid ^a   Grundy, Jim ^b   O'Leary, John ^b  

^a RICE UNIVERSITY   (United States)

^b INTEL RESEARCH   (United States)

Author keywords

Code generation; Hardware description languages; Statically typed two level languages; Synthesizability; Verilog elaboration

Indexed keywords

CODE GENERATION; HARDWARE DESCRIPTION LANGUAGES; SYNTHESIZABILITY; TWO-LEVEL LANGUAGES; VERILOG;

DESIGN; ERRORS; HARDWARE; HIGH LEVEL LANGUAGES; JAVA PROGRAMMING LANGUAGE; LINGUISTICS; NETWORK COMPONENTS; QUERY LANGUAGES; SEMANTICS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 67649521513     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1328408.1328416     Document Type: Conference Paper

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