A novel multiplication algorithm in nanotechnology

Journal of Applied Sciences

Volumn 8, Issue 14, 2008, Pages 2625-2630

  Assadi, Pooya ^a  

^a ISLAMIC AZAD UNIVERSITY   (Iran)

Author keywords

Adder; CMOS; Computer arithmetic; VLSI; Wallace

Indexed keywords

COMPUTER ARITHMETIC; CRITICAL PATHS; HIGH-SPEED LOW-POWER; MULTIPLICATION ALGORITHMS; TRANSISTOR COUNT; VLSI; WALLACE; WALLACE- TREE STRUCTURES;

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT TESTING; MULTIPLYING CIRCUITS; NANOTECHNOLOGY; NUMBERING SYSTEMS; TREES (MATHEMATICS);

FORESTRY;

EID: 67649227181     PISSN: 18125654     EISSN: 18125662     Source Type: Journal    
DOI: 10.3923/jas.2008.2625.2630     Document Type: Article

References (5)

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3. Kumar, S., T. Wollinger and C Paar, 2006. Optimum digit serial multipliers for curve-based cryptography. IEEE Trans. Comput., 55: 1306-1311.
4. Sousa, L. and R. Chaves, 2005. A universal architecture for designing efficient modulo 2 multipliers. IEEE Trans. Circuits Syst. I: Fundamental Theor. Applic., 52: 1166-1178.
5. Van, L.D. and C.C. Yang, 2005. Generalized low-error area-efficient fixed width multipliers. IEEE Trans. Circuits Syst. I: Fundamental Theor. Applic., 52: 1608-1619.