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Volumn , Issue , 2008, Pages 3434-3439

FPGA based self calibrating 40 picosecond resolution, wide range time to digital converter

Author keywords

FPGA; Picosecond; Ring oscillator; Self calibrating; TDC; TOF

Indexed keywords

FPGA; PICOSECOND; RING OSCILLATOR; SELF CALIBRATING; TDC; TOF;

EID: 67649203470     PISSN: 10957863     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NSSMIC.2008.4775078     Document Type: Conference Paper
Times cited : (34)

References (6)
  • 1
    • 11844296685 scopus 로고    scopus 로고
    • Firmware-only implementation of Time-to-Digital Converter (TDC) in field-programmable gate array (FPGA)
    • N10-2, 2003 IEEE Nuclear Science Symposium Conference Record - Nuclear Science Symposium, Medical Imaging Conference
    • Jinyuan Wu, Zonghan Shi & I. Y. Wang, "Finnware-only implementation of time-to-digital converter (TDC) in field programmable gate array (FPGA)," in Nuclear Science Symposium Conference Record, 2003 IEEE, 19-25 Oct. 2003 Page(s):177 - 181 Vol.1. (Pubitemid 40089074)
    • (2003) IEEE Nuclear Science Symposium Conference Record , vol.1 , pp. 177-181
    • Wu, J.1    Shi, Z.2    Wang, I.Y.3
  • 3
    • 84869281487 scopus 로고    scopus 로고
    • http://hep.uchicago.edu/cdf/fiisch/mstnmientation/system-summary.pdf
  • 5
    • 67649234482 scopus 로고    scopus 로고
    • FPGA-based high area efficient time-to-digital IP design
    • Lin, Min-Chuan, "FPGA-Based High Area Efficient Time-To-Digital IP Design", IEEE TENCON2006.
    • IEEE TENCON 2006
    • Min-Chuan, L.1
  • 6
    • 33846607677 scopus 로고    scopus 로고
    • An FPGA-based, 12-channel TDC and digital signal processing module For the RatCAP PET scanner
    • Oct
    • Sachin S Junnarkar. et. Al.; "An FPGA-Based, 12-Channel TDC And Digital Signal Processing Module For The RatCAP PET Scanner", IEEE Trans. Nucl. Sci, vol.2, Oct-23-29,2005.
    • (2005) IEEE Trans. Nucl. Sci , vol.2 , pp. 23-29
    • Junnarkar, S.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.