Rank identification for an analog ranked order filter

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2819-2822

  Poikonen, Jonne ^a,b   Paasio, Ari ^a  

^a UNIVERSITY OF TURKU   (Finland)

^b TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT COMPLEXITY; DEVICE MISMATCH; INPUT CURRENT; MEDIAN FILTERING; NEW APPLICATIONS; PARALLEL CURRENTS; RANKED ORDER FILTER;

IMAGE PROCESSING;

MATHEMATICAL MORPHOLOGY;

EID: 67649107509     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465213     Document Type: Conference Paper

References (6)

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2. J. Poikonen, A. Paasio, "A Ranked Order Filter Implementation for Parallel Analog Processing", IEEE Transaction on Circuits and Systems-I:Regular Papers, Vol. 51, No. 5, pp. 974-987, May 2004.
3. A. Paasio, M. Laiho, A. Kananen, K. Halonen, "An Analog Array Processor Hardware Realization with Multiple New Features", International Joint Conference on Neural Networks, Vol. 2, pp. 1952-1955, 2002.
4. J. Lazzaro, S. Ryckenbusch, M. Mahowald, C.A. Mead, "Winner-take-all networks of O(n) complexity", Adv. Neural Info. Processing Syst., Vol.1, pp. 703-711,1989.
5. S. Vlassis, S. Siskos, "Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation", Analog Integrated Circuits and Signal Processing, 34, 233-245, 2003.
6. K. Urahama, T. Nagao, "K-Winners-Take-All Circuit with O(n) Complexity", IEEE Transactions on Neural Networks, Vol.6, No.3, pp. 776-778, May 1995.