SCOPUS 정보 검색 플랫폼

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1342-1345

A scalable architecture for streaming neural information from implantable multichannel neuroprosthetic devices

(3) Thomson, Kyle E a Suhail, Yasir a Oweiss, Karim G a

a MICHIGAN STATE UNIVERSITY (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARBITRARY NUMBER; CHIP AREAS; CLOCK CYCLES; COMPUTATIONAL NODES; DATA SAMPLING; HARDWARE ARCHITECTURE; HIGH-DENSITY; LIFTING-BASED DISCRETE WAVELET TRANSFORMS; MULTI-CHANNEL; NEURAL INFORMATION; PERFORMANCE COMPARISON; REAL-TIME OPERATION; SCALABLE ARCHITECTURES;

DELAY CIRCUITS; DISCRETE WAVELET TRANSFORMS;

COMPUTER ARCHITECTURE;

EID: 67649095483 PISSN: 02714310 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ISCAS.2005.1464844 Document Type: Conference Paper

Times cited : (4)

References (7)

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2
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3
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- (2003) th IEEE Int. Conf. on Eng. in Medicine and Biology , pp. 2016-2019
- Oweiss, K.G.¹ Anderson, D.J.² Papaefthymious, M.M.³

4
- 0036538167
- A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform
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5
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- May
- H. Liao, M.Kr. Mandal, B.F. Cockburn, "Efficient architectures for 1- D and 2-D lifting-based wavelet transforms," IEEE Transactions on Signal Processing, volume: 52 , Issue: 5 , May 2004 pp:1315-1326
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6
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7
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- A Scalable Wavelet Transform VLSI Architecture for Real-Time Neural Signal Processing in Implantable Multichannel Neuroprosthetic Devices
- in review
- K. G. Oweiss, A. Mason, K. Thomson, J. Li,Y. Suhail."A Scalable Wavelet Transform VLSI Architecture for Real-Time Neural Signal Processing in Implantable Multichannel Neuroprosthetic Devices," IEEE Trans. On Circuits & Systems, in review.
- IEEE Trans. On Circuits & Systems
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.