Interfaces of high-k dielectrics on GaAs: Their common features and the relationship with Fermi level pinning (Invited Paper)

Microelectronic Engineering

Volumn 86, Issue 7-9, 2009, Pages 1529-1535

  Caymax, Matty ^a   Brammertz, Guy ^a   Delabie, Annelies ^a   Sioncke, Sonja ^a   Lin, Dennis ^a   Scarrozza, Marco ^a,b   Pourtois, Geoffrey ^a   Wang, Wei E ^a,c   Meuris, Marc ^a   Heyns, Marc ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c Kapeldreef 75   (Belgium)

Author keywords

Atomic layer deposition ALD; Atomistic modeling; GaAs MOS; High k

Indexed keywords

ATOMISTIC MODELING; BAND GAPS; BEFORE AND AFTER; COMMON FEATURES; DIELECTRIC LAYER; ELECTRICAL CHARACTERIZATION; FERMI LEVEL PINNING; FORMING GAS; GAAS; GAAS MOS; GAAS SURFACES; GROWTH PRECURSORS; GROWTH PROCESS; HIGH-K; HIGH-K DIELECTRIC; HIGH-K GATE DIELECTRICS; INTERFACE MODIFICATION; INTERFACE STATE; METAL OXIDES; PLASMA-ENHANCED ATOMIC LAYER DEPOSITION;

ATOMS; DIELECTRIC DEVICES; DIELECTRIC MATERIALS; FERMI LEVEL; FERMIONS; GALLIUM ALLOYS; GATE DIELECTRICS; GATES (TRANSISTOR); GERMANIUM; HAFNIUM COMPOUNDS; MOS CAPACITORS; PHASE INTERFACES; PLASMA DEPOSITION; SEMICONDUCTING GALLIUM; SEMICONDUCTING GERMANIUM; SEMICONDUCTOR GROWTH;

ATOMIC LAYER DEPOSITION;

EID: 67349114865     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.03.090     Document Type: Article

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