A theoretical investigation on CMOL FPGA cell assignment problem

IEEE Transactions on Nanotechnology

Volumn 8, Issue 3, 2009, Pages 322-329

  Chen, Gang ^a   Song, Xiaoyu ^b   Hu, Ping ^c  

^a Lingcore Laboratory   (United States)

^b Portland State University   (United States)

^c STMICROELECTRONICS   (Italy)

Author keywords

Cell assignment; Nanotechnology; Placement and routing; The hybrid CMOS nano circuits (CMOL)

Indexed keywords

CELL ASSIGNMENT; CELL ASSIGNMENT PROBLEM; CIRCUIT MODIFICATION; CMOL ARCHITECTURE; DOMAIN SIZE; NUMBER OF GATES; PLACEMENT AND ROUTING; THE HYBRID CMOS/NANO CIRCUITS (CMOL); THEORETICAL INVESTIGATIONS; THEORETICAL RESULT;

COMBINATORIAL CIRCUITS; NANOTECHNOLOGY; TRAVELING SALESMAN PROBLEM;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 67249153542     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2008.2011732     Document Type: Article

References (23)

1. V. Betz, "Placement for general purpose FPGAs," in Reconfigurable Computing, A. DeHon and S. Hauck, Eds. San Mateo, CA: Morgan Kauffman, 2007.
2. [2] V. Betz and J. Rose, "VPR: A new packing, placement, routing tool for FPGA research," in Proc. 7th Int. Workshop Field-Programmable Logic Appl. (FPL 1997), London, U.K.: Springer-Verlag, pp. 213-222. (Pubitemid 127118755)
3. V. Betz, J. Rose, and A. Marquard, Architecture, and CAD for DeepSubmicron FPGAs. Norwell, MA: Kluwer, 1999.
4. A. DeHon and K. Likharev, "Hybrid CMOS/nanoelectronic digital circuits: Devices, architectures, and design automation," in Proc. ICCAD, Washington, DC: IEEE Computer Society, 2005, pp. 375-382.
5. C. Dong, W. Wang, and S. Haruehanroengra, "Efficient logic architectures for CMOL nanoelectronic circuits," IET Micro. Nano. Lett., vol.1, no. 2, pp. 74-78, Dec. 2006.
6. C. Gao and D. Hammerstrom, "Cortical models onto CMOL and CMOSarchitectures and performance/price," IEEE Trans. Cirvuits Syst., vol.54, no. 11, pp. 2502-2515, Nov. 2007.
7. K. Golshan, Physical Design Essentials: An ASIC Design Implementation Perspective. Secaucus, NJ: Springer-Verlag, 2007.
8. K. Greene, "Nanotube circuits made practical," Technol, Rev., Jun. 2007.
9. J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A defecttolerant computer architecture: Opportunities for nanotechnology," Science, vol.280, no. 12, pp. 1716-1721, Jun. 1998.
10. W. Hung, C. Gao, X. Song, and D. Hammerstrom, "Defect tolerant CMOL cell assignment via satisfiability," presented at the Nanoelectronic Devices Defense Security (NANO-DDS) Conf., Crystal City, VA, 2007.
11. M. Hutton and V. Betz, "FPGA synthesis and physical design," in Electronic Design Automation for Integrated Circuits Handbook, vol 1, L. Scheffer, L. Lavagno, and G. Martin, Eds. New York/Boca Raton, FL: Taylor & Francis/CRC, 2006.
12. ITRS. (2004). International Technology Roadmap for Semiconductors emerging research devices. [Online]. Available: http://public.itrs.net
13. K. K. Likharev, "Hybrid semiconductor/nanoelectronic circuits. Invited talk in IBM Almaden, Research Center," Jun. 2007.
14. K. K. Likharev and D. B. Strukov, "CMOL technology develpment roadmap," in Proc. 4th Workshop Non-Silicon Comput., Jun. 2007, pp. 916.
15. W. Rao, A. Orailoglu, and R. Karri, "Topology aware mapping of logic functions onto nanowire-based crossbar architectures," in DAC, E. Sentovich, Ed. New York: ACM, 2006, pp. 723-726.
16. S. S. Sapatnekar, P. Saxena, and R. S. Shelar, Routing Congestion in VLSI Circuits: Estimation and Optimizatio (Series on Integrated Circuits and Systems). Secaucus, NJ: Springer-Verlag, 2007.
17. L. Scheffer, L. Lavagno, and G. Martin, Eds., Electronic Design Automation for Integrated Circuits Handbook. New York/Boca Raton, FL: Taylor & Francis/CRC, 2006.
18. N. Sherwani, Algorithms for VLSI Physical Design Automation, 3rd ed. Norwell, MA: Kluwer, 1999.
19. D. B. Strukov and K. Likharev, "CMOL FPGA circuits," in CDES, H. R. Arabnia and M. M. Eshaghian-Wilner, Eds. Las Vegas, NV: CSREA, 2006, pp. 213-219.
20. D. B. Strukov and K. K. Likharev, "CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology, vol.16, pp. 888-900, 2005.
21. [21] D. B. Strukov and K. K. Likharev, "A reconfigurable architecture for hybrid CMOS/nanodevice circuits," in Proc. 2006 ACM/SIGDA 14th Int. Symp. Field Programmable. Gate Arrays (FPGA 2006), New York: ACM, pp. 131-140. (Pubitemid 44032246)
22. D. B. Strukov and K. K. Likharev, "Reconfigurable hybrid CMOS/nanodevice circuits for image processing," IEEE Trans. Nanotechnol, vol.6, no. 6, pp. 696-710, Nov./Dec. 2007.
23. K. Wang and A. Balandin, Eds., The Handbook of Semiconductor Nanostructures and Nanodevices. Valencia, CA: America Scientific, Oct. 2005.