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1
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0038350781
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High-Density packaging technologies on silicon substrate
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New Orleans, LA
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M. Akazawa, S. Kuramochi, T. Maruyama, K. Nakayama, A. Takano, M. Yamaguchi, and Y. Fukuoka, "High-Density packaging technologies on silicon substrate," in Proc. 53rd Electron. Compon. Technol. Conf. New Orleans, LA, 2003, pp. 647-651.
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(2003)
Proc. 53rd Electron. Compon. Technol. Conf
, pp. 647-651
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Akazawa, M.1
Kuramochi, S.2
Maruyama, T.3
Nakayama, K.4
Takano, A.5
Yamaguchi, M.6
Fukuoka, Y.7
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2
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67149112171
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High density wiring technology and evaluation with Cu/photosensitive-BCB multilayer structure
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Tokyo, Japan
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K. Nakayama, T. Mori, M. Yamaguchi, M. Akazawa, S. Kuramochi, A. Takano, and Y. Fukuoka, "High density wiring technology and evaluation with Cu/photosensitive-BCB multilayer structure," in Proc. Int. Conf. Electron. Packag., Tokyo, Japan, 2003, pp. 47-52.
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(2003)
Proc. Int. Conf. Electron. Packag
, pp. 47-52
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Nakayama, K.1
Mori, T.2
Yamaguchi, M.3
Akazawa, M.4
Kuramochi, S.5
Takano, A.6
Fukuoka, Y.7
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3
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67149128763
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Development of a new interposer including embedded film passive components
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presented at the, Atlanta, GA
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T. Mori, K. Nakamura, M. Yamaguchi, K. Nakayama, M. Akazawa, S. Kuramochi, K. Suzuki, and Y. Fukuoka, "Development of a new interposer including embedded film passive components," presented at the Int. Workshop SOP, SIP, SOC (3S) Electronics Technologies, Atlanta, GA, 2005.
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(2005)
Int. Workshop SOP, SIP, SOC (3S) Electronics Technologies
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Mori, T.1
Nakamura, K.2
Yamaguchi, M.3
Nakayama, K.4
Akazawa, M.5
Kuramochi, S.6
Suzuki, K.7
Fukuoka, Y.8
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4
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67149091254
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Development of PWB with embedded chip passive components
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Osaka, Japan
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K. Sasaoka, N. Morioka, and Y. Fukuoka, "Development of PWB with embedded chip passive components," in Proc. 15th Micro Electron. Symp., Osaka, Japan, 2005, pp. 169-172.
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(2005)
Proc. 15th Micro Electron. Symp
, pp. 169-172
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Sasaoka, K.1
Morioka, N.2
Fukuoka, Y.3
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5
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67149133791
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Development of PWB with embedded active devices and chip passive components
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Kobe, Japan
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K. Sasaoka, T. Motomura, N. Morioka, and Y. Fukuoka, "Development of PWB with embedded active devices and chip passive components," in Proc. 17th Micro Electron. Symp., Kobe, Japan, 2007, pp. 159-162.
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(2007)
Proc. 17th Micro Electron. Symp
, pp. 159-162
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Sasaoka, K.1
Motomura, T.2
Morioka, N.3
Fukuoka, Y.4
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6
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67149132113
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Development of buried bump interconnection technology with embedded passive devices
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Tokyo, Japan
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H. Shibasaki, T. Serizawa, T. Kihara, K. Sasaoka, N. Morioka, Y.Yamaguchi, K. Shinozaki, and Y. Fukuoka, "Development of buried bump interconnection technology with embedded passive devices," in Proc. Int. Conf. Electron. Packag., Tokyo, Japan, 2004, pp. 113-118.
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(2004)
Proc. Int. Conf. Electron. Packag
, pp. 113-118
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Shibasaki, H.1
Serizawa, T.2
Kihara, T.3
Sasaoka, K.4
Morioka, N.5
Yamaguchi, Y.6
Shinozaki, K.7
Fukuoka, Y.8
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7
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67149119611
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Relationship of printed embedded passive device size to electronic features
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Tokyo, Japan
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A. Furuya, H. Nomura, K. Komoto, and K. Okada, "Relationship of printed embedded passive device size to electronic features," in Proc. Int. Conf. Electron. Packag., Tokyo, Japan, 2007, pp. 157-161.
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(2007)
Proc. Int. Conf. Electron. Packag
, pp. 157-161
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Furuya, A.1
Nomura, H.2
Komoto, K.3
Okada, K.4
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8
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24644520442
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High Q, tunable thin film capacitors and geometrical effects on device performance at microwave frequencies
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J. Park, J. Lu, S. Stemmer, and R. A. York, "High Q, tunable thin film capacitors and geometrical effects on device performance at microwave frequencies," in Proc. 55th Electron. Compon. Technol. Conf., 2005, pp. 776-778.
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(2005)
Proc. 55th Electron. Compon. Technol. Conf
, pp. 776-778
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Park, J.1
Lu, J.2
Stemmer, S.3
York, R.A.4
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9
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24644438843
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Dual process dielectric formation for decoupling capacitors on flexible substrates
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R. Raghuveer, S. L. Burkett, L. W. Schaper, and R. K. Ulrich, "Dual process dielectric formation for decoupling capacitors on flexible substrates," in Proc. 55th Electron. Compon. Technol. Conf., 2005, pp. 1569-1573.
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(2005)
Proc. 55th Electron. Compon. Technol. Conf
, pp. 1569-1573
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Raghuveer, R.1
Burkett, S.L.2
Schaper, L.W.3
Ulrich, R.K.4
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10
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33845587400
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Novel substrate with combined embedded capacitance and resistance for better electrical performance and higher integration
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San Diego, CA
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J. Andresakis and P. Pramanik, "Novel substrate with combined embedded capacitance and resistance for better electrical performance and higher integration," in Proc. 56th Electron. Compon. Technol. Conf., San Diego, CA, 2006, pp. 1544-1547.
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(2006)
Proc. 56th Electron. Compon. Technol. Conf
, pp. 1544-1547
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Andresakis, J.1
Pramanik, P.2
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