Digital compensation of dynamic acquisition errors at the front-end of high-performance A/D converters

IEEE Journal on Selected Topics in Signal Processing

Volumn 3, Issue 3, 2009, Pages 499-508

  Nikaeen, Parastoo ^a   Murmann, Boris ^a  

^a Stanford University   (United States)

Author keywords

Analog digital conversion; Calibration; Error compensation; Nonlinearities; Signal sampling

Indexed keywords

A/D CONVERTER; ANALOG-DIGITAL CONVERSION; DIGITAL COMPENSATION; DIGITAL CORRECTION; DYNAMIC ERROR; HIGH RESOLUTION; HIGH-SPEED; INPUT AND OUTPUTS; INPUT FREQUENCY; LEAST SQUARES; LIMITING FACTORS; NON-IDEALITIES; NONLINEARITIES; NYQUIST; POST-PROCESSING SCHEME; SIGNAL SAMPLING; SIMULATION RESULT; TRACK AND HOLD CIRCUITS; TRACK-AND-HOLD; TRAINING SIGNAL; VOLTERRA SERIES;

CALIBRATION; CURVE FITTING; ELECTRIC CONVERTERS; LINEARIZATION;

ERROR COMPENSATION;

EID: 66949133589     PISSN: 19324553     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSTSP.2009.2020575     Document Type: Article

References (22)

1. A. M. A. Ali et al., "A 14 bit 125 Ms/s IF/RF sampling pipelined A/D converter," in Proc. CICC, Sep. 2005, pp. 391-394.
2. H. Pan et al., "A 3.3 V, 12 b, 50 MSample/s A/D converter in 0.6 um CMOS with over 80 dB SFDR," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 176-1780, Dec. 2000.
3. B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.
4. Y. Chiu et al., "Least mean square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Trans. Circuits Syst. I, vol. 51, no. 1, pp. 38-46, Jan. 2004.
5. C. Grace, P. J. Hurst, and S. H. Lewis, "A 12 b 80MS/s pipelined ADC with bootstrapped digital calibration," in ISSCC Dig. Tech. Papers Feb. 2004, pp. 460-461.
6. J. Tsimbinos, "Identification and Compensation of Nonlinear Distortion," Ph.D. dissertation, Univ. South Australia, Adelaide, Feb. 1995.
7. H. Lundin, "An Introduction to ADC Error Correction," Rep., Royal Inst. Technol., Stockholm, Sweden, May 2005.
8. J. Tsimbinos and K. V. Lever, "Application of higher order statistics to modeling, identification and cancellation of nonlinear distortion in high-speed samplers and analog-to-digital converters using Volterra and Wiener models," in Proc. IEEE Signal Processing Workshop on Higher-Order Statistics, Jun. 1993, pp. 379-383.
9. E. Balestrieri et al., "A state of the art on ADC error compensation methods," IEEE Trans. Instrum. Meas., vol. 54, no. 4, pp. 1388-1394, Aug. 2005.
10. P. Wambacq and W. M. Sansen, Distortion Analysis of Analog Integrated Circuits. Boston, MA: Kluwer, 1998.
11. M. Hasler and G. Kubin, "Mixed-domain system representation using Volterra series," in Proc. Int. Symp. Circuits and Systems, May 2008, pp. 572-575.
12. M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems Malabar, FL: Krieger, 1989, Reprint Edition.
13. M. Schetzen, "Theory of pth-order inverses of nonlinear systems," IEEE Trans. Circuits Syst., vol. 23, no. 5, pp. 285-291, May 1976.
14. National Semiconductor, ADC14155 Datasheet [Online]. Available: http:// www.national.com/pf/DC/ADC14155.html#Datasheet
15. P. Nikaeen and B. Murmann, "Digital correction of dynamic track-and-hold errors providing SFDR > 83 dB up to fin = 470 MHz," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2008, pp. 161-164.
16. A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
17. "Medici User Guide," ver. W-2004.09, Synopsis, Sep. 2004.
18. "Dessis Manual," ver. ISE TCAD Release 10.0, Synopsis, 2004.
19. F. H. Irons, "Dynamic characterization and compensation of analog to digital converters," in Proc. IEEE Int. Symp. Circuits Systems, 1986, vol. 3, pp. 1273-1277.
20. D. M. Hummels, R. W. Cook, and F. H. Irons, "Discrete-time dynamic compensation of analog-to-digital converters," in Proc. IEEE Int. Symp. Circuits and Systems, 1993, pp. 1144-1147.
21. T. A. Rebold and F. H. Irons, "A phase-plane approach to the compensation of high-speed analog-to-digital converters," in Proc. IEEE Int. Symp. Circuits and Systems, 1987, pp. 455-458.
22. M. H. Hayes, Statistical Digital Signal Processing and Modeling. New York: Wiley, 1996.