Low-power, high-performance analog neural branch prediction

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue 2008 PROCEEDINGS, 2008, Pages 447-458

  Amant, Renée St ^a   Jiménez, Daniel A ^b   Burger, Doug ^c  

^a University of Texas at Austin   (United States)

^b University of Texas at San Antonio   (United States)

^c MICROSOFT RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM TECHNOLOGY; ACCURATE PREDICTION; ANALOG CIRCUITRY; ANALOG IMPLEMENTATION; CURRENT SUMMATION; DEVICE VARIATIONS; DIGITAL IMPLEMENTATION; LOW POWER; LOW POWER PROCESSORS; NEURAL BRANCH PREDICTION; NEURAL PREDICTORS; PREDICTION COMPUTATION; REDUCED COST; SOFT ERROR; TRANSISTOR SIZE;

ERROR CORRECTION; TABLE LOOKUP;

DIGITAL DEVICES;

EID: 66749140113     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2008.4771812     Document Type: Conference Paper

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