System in package (SiP) with reduced parasitic inductance for future voltage regulator

IEEE Transactions on Power Electronics

Volumn 24, Issue 6, 2009, Pages 1547-1553

  Hashimoto, Takayuki ^a   Shiraishi, Masaki ^a   Akiyama, Noboru ^a   Kawashima, Tetsuya ^a   Uno, Tomoaki ^b   Matsuura, Nobuyoshi ^b  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Low parasitic inductance; Packaging; Power FETs; Voltage regulator (VR)

Indexed keywords

BREAKDOWN VOLTAGE; CONDUCTION LOSS; DISCRETE PACKAGE; DRAIN VOLTAGE; DRIVER IC; LOW PARASITIC INDUCTANCE; LOW-PARASITIC; MIXED MODE SIMULATION; MOS-FET; MOSFETS; PARASITIC INDUCTANCES; POWER FETS; POWER-LOSSES; SWITCHING LOSS; SWITCHING NOISE; SYSTEM IN PACKAGE;

CAPACITANCE; ELECTRIC CONDUCTIVITY; ELECTRIC POTENTIAL; INDUCTANCE; INTERNET PROTOCOLS; IONIZATION OF GASES; MESFET DEVICES; MOSFET DEVICES; VOLTAGE CONTROL; VOLTAGE STABILIZING CIRCUITS;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 66749097690     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2009.2013225     Document Type: Article

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