Acceleration of DCT processing with massive-parallel memory-embedded SIMD matrix processor

IEICE Transactions on Information and Systems

Volumn E90-D, Issue 8, 2007, Pages 1312-1315

  Kumaki, Takeshi ^a   Ishizaki, Masakatsu ^a   Koide, Tetsushi ^a   Mattausch, Hans Jürgen ^a   Kuroda, Yasuto ^b   Noda, Hideyuki ^b   Dosaka, Katsumi ^b   Arimoto, Kazutami ^b   Saito, Kazunori ^b  

^a HIROSHIMA UNIVERSITY   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Bit serial and word parallel; DCT; Fast DCT; Matrix processing engine; SIMD

Indexed keywords

COMPUTER ARCHITECTURE; COSINE TRANSFORMS; DISCRETE COSINE TRANSFORMS; ENGINES; IMAGE COMPRESSION; MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; PROCESSING;

BIT-SERIAL; DISCRETE COSINE TRANSFORM(DCT); FAST DCT; FLEXIBLE SWITCHING; PARALLEL OPERATIONS; PROCESSING ELEMENTS; PROCESSING ENGINE; SIMD;

IMAGE PROCESSING;

EID: 66449118870     PISSN: 09168532     EISSN: 17451361     Source Type: Journal    
DOI: 10.1093/ietisy/e90-d.8.1312     Document Type: Article

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