Leakage minimization technique for nanoscale CMOS VLSI

IEEE Design and Test of Computers

Volumn 24, Issue 4, 2007, Pages 322-330

  Kim, Kyung Ki ^a   Kim, Yong Bin ^a   Choi, Minsu ^b   Park, Nohpill ^c  

^a Northeastern University   (United States)

^b Architectural and Environmental Engineering   (United States)

^c Department of Computer Science   (United States)

Author keywords

Cell characterization; Gate tunneling current; Input pattern generation; Leakage power; Nanometer CMOS; Subthreshold leakage current

Indexed keywords

GATE-TUNNELING CURRENT; INPUT PATTERN GENERATION; LEAKAGE POWER; NANOMETER CMOS; SUBTHRESHOLD LEAKAGE CURRENT;

ELECTRON TUNNELING; TUNNELING (EXCAVATION);

LEAKAGE CURRENTS;

EID: 65349085835     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2007.111     Document Type: Article

References (12)

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