Self-Aligned n-channel MOSFET on InP and in 0.53Ga 0.47As using physical vapor deposition HTO 2 and silicon interface passivation layer

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 2008, Pages 91-92

  Ok, Injo ^d   Kim, H ^d   Zhang, M ^d   Zhu, F ^d   Zhao, H ^d   Park, S ^d   Yum, J ^d   Garcia, Domingo ^a   Majhi, Prashant ^a   Goel, N ^b   Tsai, W ^b   Gaspe, C K ^c   Santos, M B ^c   Lee, Jack C ^c  

^a SEMATECH   (United States)

^b INTEL CORPORATION   (United States)

^c University of Oklahoma   (United States)

^d The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 64849091035     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2008.4800749     Document Type: Conference Paper

References (1)

1. Byoung Hun Lee et al., IEDM Tech. Cig., 1999, pp. 133-136.