Contact resistance reduction of Pt-incorporated NiSi for continuous CMOS scaling ∼ atomic level analysis of Pt/B/As distribution within silicide films ∼

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Sonehara, Takeshi ^a   Hokazono, Akira ^a   Akutsu, Haruko ^a   Sasaki, Tomokazu ^a   Uchida, Hiroshi ^a   Tomita, Mitsuhiro ^a   Tsujii, Hideji ^a   Kawanaka, Shigeru ^a   Inaba, Satoshi ^a   Toyoshima, Yoshiaki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LEVEL ANALYSIS; CMOS SCALING; ELECTRICAL PROPERTIES; ELECTRODE ATOM PROBES; GRAIN SIZES; N-MOSFETS; NICKEL SILICIDES; P-MOSFETS; RESISTANCE REDUCTIONS; SI FILMS; SILICIDE FILMS; SIZE MINIATURIZATIONS; THERMAL STABILITIES;

CONTACT RESISTANCE; ELECTRIC PROPERTIES; ELECTRON DEVICES; GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; SILICIDES;

PLATINUM;

EID: 64549152383     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796851     Document Type: Conference Paper

References (6)

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4. Haruko Akutsu, Hiroshi Uchida, Kazuhiko Nakamura, Toshihiko Iinuma and Kyoichi Suguro, SSDM, (2007), p296
5. T. P. Noran et al., J. Appl. Phys., Vol.71, No.2, p.720 (1992)
6. Takao Marukame et al., to be published in IEDM (2008).