A 300 nW, 7 ppm/°C CMOS voltage reference circuit based on subthreshold MOSFETs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 95-96

  Ueno, Ken ^a   Hirose, Tetsuya ^b   Asai, Tetsuya ^a   Amemiya, Yoshihito ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

^b KOBE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ABSOLUTE ZERO TEMPERATURES; CMOS VOLTAGE REFERENCES; LOW-POWER DISSIPATIONS; LSI CHIPS; MOSFETS; ON-CHIP PROCESS; POWER SUPPLIES; POWER-SUPPLY REJECTION RATIOS; REFERENCE VOLTAGES; STANDARD CMOS PROCESS; SUB THRESHOLDS; TEMPERATURE CO-EFFICIENT; ULTRA-LOW-POWER;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER TRANSMISSION NETWORKS; ELECTRIC POWER UTILIZATION; POWER SUPPLY CIRCUITS; PROCESS MONITORING; THRESHOLD VOLTAGE; VOLTAGE MEASUREMENT;

MOSFET DEVICES;

EID: 64549137193     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796449     Document Type: Conference Paper

References (5)

1. K. Ueno, et, al., IEEE JSSC, pp. 798-803, 2007.
2. G. De Vita, et, al., IEEE JSSC, pp. 1536 - 1542, 2007.
3. K. N. Leung, et, al., IEEE JSSC, pp. 146 - 150, 2003.
4. G. Giustolisi, et, al., IEEE JSSC, pp. 151 - 154, 2003.
5. K. Ueno, et, al., Proc. of the 34th ESSCIRC, pp. 398-401, 2008.