Nanowire FETs for Low Power CMOS Applications Featuring Novel Gate-All-Around Single Metal FUSI Gates with Dual φ m and v T Tune-ability

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Jiang, Y ^a,b   Liow, T Y ^a   Singh, N ^a   Tan, L H ^a   Lo, G Q ^a   Chan, D S H ^b   Kwong, D L ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE PERFORMANCE; GATE-ALL-AROUND; INDUCED STRESS; LOW POWER CMOS; METAL GATES; NANOWIRE FETS;

ELECTRON DEVICES; FIELD EFFECT TRANSISTORS; NANOWIRES;

MESFET DEVICES;

EID: 64549121032     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796836     Document Type: Conference Paper

References (11)

1. N. Singh et al., IEDM Tech. Dig., 2006, pp. 547-550
2. K.H. Yeo et al., IEDM Tech. Dig., 2006, pp.539-542
3. S.D. Suk et al., IEDM Tech. Dig., 2005, pp.717-720.
4. Y. Jiang et al., VLSI Symp. Tech. Digest, 2008, pp. 34-35
5. J. Kedzierski et al., IEEE TED, vol. 52, No. 1, 2005, pp. 39 - 46
6. T.-Y. Liow et al., SSDM, 2007, pp. 872-873
7. H. Fukutome et al, VLSI Symp. Tech. Digest, 2008, pp. 150-151
8. H. Nakamura et al., VLSI Symp. Tech. Digest, 2006, pp. 158-159
9. T. Hayashi et al., IEDM Tech. Dig, 2006, pp.247-250
10. C.-H. Jan et al., IEDM Tech. Dig., 2005, pp.60-63
11. A. Steegen et al., IEDM Tech. Dig, 2005, pp.64-67