Universality of interface trap generation and its impact on iD degradation in strained/unstrained PMOS transistors under NBTI stress

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Islam, A E ^a   Lee, J H ^a   Wu, W H ^a   Oates, A ^b   Alam, M A ^b  

^a PURDUE UNIVERSITY   (United States)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS SCALING; INTERFACE TRAP GENERATIONS; PMOS TRANSISTORS; STRAINED TECHNOLOGIES; STRAINED TRANSISTORS;

ELECTRON DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; THERMODYNAMIC STABILITY;

TRANSISTORS;

EID: 64549102456     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796626     Document Type: Conference Paper

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