A unified 7.5nm dash-type confined cell for high performance PRAM device

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Im, D H ^a   Lee, J I ^a   Cho, S L ^a   An, H G ^a   Kim, D H ^a   Kim, I S ^a   Park, H ^a   Ahn, D H ^a   Horii, H ^a   Park, S O ^a   Chung, U In ^a   Moon, J T ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH RELIABILITIES; PHYSICAL LIMITS; PROGRAMMING TIME; RESET CURRENTS;

ELECTRON DEVICES; PHASE CHANGE MATERIALS; PULSE CODE MODULATION;

CHEMICAL VAPOR DEPOSITION;

EID: 64549094128     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796654     Document Type: Conference Paper

References (4)

1. S. L. Cho, J. H. Yi, Y. H. Ha, B. J. Kuh, C. M. Lee, J. H. Park, S.D. Nam, H. Horii, B. O. Cho, K. C. Ryoo, S. O. Park, H. S. Kim, U.-I. Chung, J. T. Moon, and B. I. Ryu, "Highly scalable on axis confined cell structure for high density PRAM beyond 256Mb," Symp. VLSI Tech dig., pp. 96-97, 2005.
2. J. I. Lee, S. L. Cho, Y. L. Park, B. J. Bae, J. H. Park, J. S. Park, H. G. An, J. S. Bae, D. H. Ahn, Y. T. Kim, H. Horii, S. A. Song, J. C. Shin, S. O. Park, H. S. Kim, U.-I. Chung, J. T. Moon, and B.I. Ryu, "Highly scalable phase change memory with CVD GeSbTe for sub 50nm generation," Symp. VLSI Tech dig., pp. 102-103, 2007.
3. Ugo Russo, Andrea Redaelli, and Andrea L. Lacaita, "Modeling of programming and read performance in phase-change memory - Part I: Cell optimization and scaling," IEEE Trans. Electron Devices, vol 55, no.2, pp.506-514, February 2008.
4. S. J. Ahn, Y. J. Song, C. W. Jeong, J. M. Shin, Y. Fai, Y. N. Hwang, S. H. Lee, K. C. Ryoo, S. Y. Lee, J. H. Park, H. Horii, Y. H. Ha, J. H. Yi, B. J. Kuh, G. H. Koh, G. T. Jeong, H. S. Jeong, Kinam Kim, and B. I. Ryu, "Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond," IEDM Tech. Dig., pp. 907-910, 2004.