메뉴 건너뛰기




Volumn 2, Issue 2, 1997, Pages 98-122

Functional design for testability of control-dominated architectures

Author keywords

Functional testing; Interacting FSMs

Indexed keywords


EID: 6444235838     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/253052.253064     Document Type: Article
Times cited : (4)

References (27)
  • 2
    • 0004931620 scopus 로고
    • Finite state machine synthesis with embedded test function
    • AGRAWAL, V. D. AND CHENG, K. T. 1990. Finite state machine synthesis with embedded test function. J. Electron. Testing: Theory Appl. 1, 221-228.
    • (1990) J. Electron. Testing: Theory Appl. , vol.1 , pp. 221-228
    • Agrawal, V.D.1    Cheng, K.T.2
  • 3
    • 0017983865 scopus 로고
    • Binary decision diagrams
    • AKERS, S. B. 1978. Binary decision diagrams. IEEE Trans. Comput. C-27, 6 (June) 957-959.
    • (1978) IEEE Trans. Comput. , vol.C-27 , Issue.6 JUNE , pp. 957-959
    • Akers, S.B.1
  • 4
    • 33746662098 scopus 로고
    • Two-dimensional sequential array architectures: Design for testability and reconfiguration issues
    • BOLCHINI, C., FUMMI, F, AND SCIUTO, D. 1993. Two-dimensional sequential array architectures: Design for testability and reconfiguration issues. J. Microelectron. Syst. Integration 1, 3/4, 209-220.
    • (1993) J. Microelectron. Syst. Integration , vol.1 , Issue.3-4 , pp. 209-220
    • Bolchini, C.1    Fummi, F.2    Sciuto, D.3
  • 6
    • 0025419945 scopus 로고
    • A partial scan method for sequential circuits with feedback
    • CHENG, K. T. AND AGRAWAL, D. D. 1990. A partial scan method for sequential circuits with feedback. IEEE Trans. Comput. C-39, 4 (April), 544-548.
    • (1990) IEEE Trans. Comput. , vol.C-39 , Issue.4 APRIL , pp. 544-548
    • Cheng, K.T.1    Agrawal, D.D.2
  • 8
    • 0027632531 scopus 로고
    • Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration
    • CHO, H., HACHTEL, G. D., AND SOMENZI, F. 1993. Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration. IEEE Trans. Comput. 12, 7 (July), 935-945.
    • (1993) IEEE Trans. Comput. , vol.12 , Issue.7 JULY , pp. 935-945
    • Cho, H.1    Hachtel, G.D.2    Somenzi, F.3
  • 9
    • 33746670431 scopus 로고    scopus 로고
    • DEVADAS, S., GHOSH, A., AND KEUTZER, K. 1994. McGraw-Hill, New York, NY
    • DEVADAS, S., GHOSH, A., AND KEUTZER, K. 1994. McGraw-Hill, New York, NY.
  • 12
    • 0029474937 scopus 로고
    • Testable synthesis of highly complex control devices
    • FUMMI, F., ROVATI, U., AND SCIUTO, D. 1995. Testable synthesis of highly complex control devices. In Proceedings of EURODAC, 117-122.
    • (1995) Proceedings of EURODAC , pp. 117-122
    • Fummi, F.1    Rovati, U.2    Sciuto, D.3
  • 13
    • 0028749370 scopus 로고
    • Test generation for stuck-at and gate-delay faults in sequential circuits: A mixed functional/structural method
    • FUMMI, F., SCIUTO, D., AND SERRA, M. 1994. Test generation for stuck-at and gate-delay faults in sequential circuits: A mixed functional/structural method. In Proceedings of the IEEE International Workshop on DFT, 254-262.
    • (1994) Proceedings of the IEEE International Workshop on DFT , pp. 254-262
    • Fummi, F.1    Sciuto, D.2    Serra, M.3
  • 14
    • 33746769610 scopus 로고
    • Sequential logic minimization based on functional testability
    • FUMMI, F., SCIUTO, D., AND SERRA, M. 1995. Sequential logic minimization based on functional testability. In Proceedings of ED&TC, 207-211.
    • (1995) Proceedings of ED&TC , pp. 207-211
    • Fummi, F.1    Sciuto, D.2    Serra, M.3
  • 15
    • 0029506902 scopus 로고
    • Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
    • GHOSH, I., RAGHUNATHAN, A., AND JHA, N. K. 1995. Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. In Proceedings of IEEE ICCD, 173-179.
    • (1995) Proceedings of IEEE ICCD , pp. 173-179
    • Ghosh, I.1    Raghunathan, A.2    Jha, N.K.3
  • 17
    • 0029394261 scopus 로고
    • A partition and resynthesis approach to testable design of large circuits
    • KANJILAL, S., CHAKRADHAR, S. T., AND AGRAWAL, V. D. 1995a. A partition and resynthesis approach to testable design of large circuits. IEEE Trans. CAD/ICAS 14, 10 (Oct.), 1268-1276.
    • (1995) IEEE Trans. CAD/ICAS , vol.14 , Issue.10 OCT , pp. 1268-1276
    • Kanjilal, S.1    Chakradhar, S.T.2    Agrawal, V.D.3
  • 18
    • 0029378225 scopus 로고
    • Test function embedding algorithms with application to interconnected finite state machines
    • KANJILAL, S., CHAKRADHAR, S. T., AND AGRAWAL, V. D. 1995b. Test function embedding algorithms with application to interconnected finite state machines. IEEE Trans. CAD/ ICAS 14, 9 (Sept.), 1115-1127.
    • (1995) IEEE Trans. CAD/ ICAS , vol.14 , Issue.9 SEPT , pp. 1115-1127
    • Kanjilal, S.1    Chakradhar, S.T.2    Agrawal, V.D.3
  • 19
    • 0025561326 scopus 로고
    • On determining scan flip-flops in partial-scan designs
    • LEE, D. H. AND REDDY, S. M. 1990. On determining scan flip-flops in partial-scan designs. In Proceedings of the IEEE ICCAD, 322-325.
    • (1990) Proceedings of the IEEE ICCAD , pp. 322-325
    • Lee, D.H.1    Reddy, S.M.2
  • 22
    • 33645157156 scopus 로고
    • Heuristics for the placement of flip-flops in partial scan designs and the placement of signal bosters in lossy circuits
    • PAIR, D., REDDY, S. M., AND SAHNI, S. 1993. Heuristics for the placement of flip-flops in partial scan designs and the placement of signal bosters in lossy circuits. In Proceedings of the International Conference on VLSI Design, 45-50.
    • (1993) Proceedings of the International Conference on VLSI Design , pp. 45-50
    • Pair, D.1    Reddy, S.M.2    Sahni, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.