A study on an asic design technique for digital protective relays

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 3910-3913

  Seo, Jong Wan ^a   Shin, Myong Chul ^a  

^a Sungkyunkwan University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ASIC DESIGN; ASIC TECHNOLOGIES; CHANNEL SOURCE; CMOS TECHNOLOGY; CORDIC PROCESSORS; DIE SIZE; DIGITAL PROTECTIVE RELAY; EXPONENTIATION; HIGH-SPEED PROCESSING; INSTRUCTION SET ARCHITECTURE; RE-PROGRAMMABILITY; SAMPLING RATES; VLSI DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS;

RELAY PROTECTION;

EID: 63649127328     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465485     Document Type: Conference Paper

References (7)

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7. T. S. Sindu, M. S. Sachdev and H. C. Wood, "A computer aided design tool for developing digital controllers and relays", IEEE trans. on Industry Applications, Vol. 28, No. 6, pp. 1376-1383, 1992.