The EKV 3.0 compact MOS transistor model: Accounting for deep-submicron aspects

2002 International Conference on Modeling and Simulation of Microsystems - MSM 2002

Volumn , Issue , 2002, Pages 670-673

  Bucher, Matthias ^a,b   Enz, Christian ^c,d   Krummenacher, François ^d   Sallese, Jean M ^d   Lallement, Christophe ^e   Porret, Alain S ^f  

^a NATIONAL TECHNICAL UNIVERSITY OF ATHENS   (Greece)

^b Smart Silicon Systems SA   (Switzerland)

^c Swiss Ctr Electron Microtechniques   (Switzerland)

^d EPFL   (Switzerland)

^e ERM PHASE   (France)

^f Xceive Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE; TRANSCONDUCTANCE;

EKV MODELS; NORMALIZATION; SUBMICRONS; TRANSISTOR MODELS;

MOSFET DEVICES;

EID: 6344292512     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Y. Tsividis, "Operation and Modeling of the MOS Transistor", McGraw-Hill, 2nd Edition, 1999.
2. C. C. Enz, F. Krummenacher, E. A. Vittoz, "An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications", Analog Int. Circ. Signal Proc. J., Vol. 8, pp. 83-114, 1995.
3. A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, "An Explicit Physical Model for Long-channel MOS Transistor Including Small-signal Parameters", Solid State Electronics, Vol. 38, N° 11, pp. 1945-1952, 1995.
4. M. Bucher, C. Lallement, C. Enz, F. Théodoloz, F. Krummenacher, "The EPFL-EKV 2.6 MOSFET Model Equations for Simulation", Technical Report, EPFL, June 1997; 〈http://legwww.epfl.ch/ekv/〉.
5. M. Bucher, C. Lallemem, C. Enz, F. Théodoloz, F. Krummenacher, "Scalable GM/I Based MOSFET Model", Int. Semicond. Device Research Symp., pp. 615-618, Dec. 1997.
6. A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, "An MOS Transistor Model for Analog Circuit Design", IEEE Journ. Solid-State Circuits, Vol. 33, N° 10, pp. 1510-1519, Oct. 1998.
7. M. Bucher, J.-M. Sallese, C. Lallement, W. Grabinski, C. Enz, F. Krummenacher, "Extended Charges Modeling For Deep Submicron CMOS", Int. Semicond. Device Research Symp., pp. 397-400, December 1999.
8. M. Bucher, "Analytical Modelling of the MOS Transistor for Circuit Simulation", Ph. D. Thesis N° 2114 (1999), Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland.
9. J.-M. Sallese, M. Bucher, C. Lallement, "Improved Analytical Modeling of Polysilicon Depletion in MOSFETs for Circuit Simulation", Solid State Electronics, Vol. 44, N° 6, pp. 905-912, June 2000.
10. J.-M. Sallese, W. Grabinski, A.-S. Porret, M. Bucher, C. Lallement, F. Krummenacher, C. Enz, P. Fazan, "Advancements in DC and RF MOSFET Modeling with the EPFL-EKV Charge-Based Model", Proc. 8th Int. Conf. on Mixed-Signal Design, June 2001.
11. M. Bucher, J.-M. Sallese, C. Lallement, "Accounting for Quantum Effects and Polysilicon Depletion in an Analytical Design-Oriented MOSFET Model", Simulation of Semicond. Processes and Devices 2001, pp. 296-299, Ed. D. Tsoukalas, C. Tsamis, Springer 2001.
12. C. Enz, M. Bucher, A.-S, Porret, J. M. Sallese, F. Krummenacher, "The Foundations of the EKV MOS Transistor Charge-Based Model", WCM-MSM, April 2002, in this issue.