Circuit layout evolution: An evolvable hardware approach

IEE Colloquium (Digest)

Volumn , Issue 33, 1999, Pages 11-14

  Kalganova, Tatiana ^a   Miller, Julian F ^a  

^a EDINBURGH NAPIER UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

GENES; GENETIC ALGORITHMS; GENETIC ENGINEERING; LOGIC CIRCUITS;

CIRCUIT STRUCTURES; EVOLVABLE HARDWARE (EH); LOGIC NETWORKS;

INTEGRATED CIRCUIT LAYOUT;

EID: 6344291809     PISSN: 09633308     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (9)

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2. Miller J. F., Thomson P., and Fogarty T. C. (1997). Designing Electronic Circuits Using Evolutionary Algorithms. Arithmetic Circuits: A Case Study. in Genetic Algorithms and Evolution Strategies in Engineering and Computer Science, Eds. D. Quagliarella, et al., Wiley.
3. Thompson A. (1997). An evolved circuit, intrinsic in silicon, entwined with physics, in Proc. of the 1st Int. Conf. on Evolvable Systems: From Biology to Hardware (ICES96), Lecture Notes in Computer Science, Eds. Higuchi T., et al. Vol. 1259, Springer-Verlag, pp.390-405.
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7. th Int. Conf. on Parallel Problem Solving from Nature (PPSNV), Lecture Notes in Computer Science, Vol. 1498, Springer-Verlag, pp. 927-936.
8. Kalganova, T., J. Miller and N. Lipnitskaya (1998). Multiple-Valued Combinational Circuits Synthesized using Evolvable Hardware Approach in Proc. of the 7th Workshop on Post-Binary Ultra Large Scale Integration Systems (ULSI'98) in association with ISMVL'98, Japan. IEEE Press.
9. nd Int. Conf. on Evolvable Systems (ICES'98). Switzerland, Eds. M. Sipper, et al, Springer-Verlag, pp. 78-89.