Modeling of accumulation MOS capacitors for analog design in digital VLSI processes

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 6, Issue , 1999, Pages

  Pavan, Shanthi ^a   Tsividis, Yannis ^a   Nagaraj, Krishnaswamy ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HARMONIC DISTORTION; POLYSILICON GATE DEPLETION EFFECT;

ELECTRIC DISTORTION; PIECEWISE LINEAR TECHNIQUES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; VLSI CIRCUITS;

MOS CAPACITORS;

EID: 6344270950     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (6)

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2. ndedition, McGraw Hill Book Company, New York, New York; 1999.
3. N.D. Arora, R. Rios and C.-L. Huang, "Modeling the polysilicon-gate depletion in MOS structures," IEEE Electron Device Letters, Vol. ED-39, pp. 932-938, 1994.
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5. R. Rios and N.D. Arora, "Determination of ultra-thin gate oxide thickness for CMOS structures using quantum effects," IE DM Technical Digest, pp. 613-616, 1994.
6. F. Stern and W.E. Howard, "Properties of semiconductor surface inversion layers in the electric quantum limit," Physical Revue B, Vol. 163, pp. 816-835, 1967.