메뉴 건너뛰기




Volumn 4, Issue , 2004, Pages 2182-2188

Two novel encoding strategies based genetic algorithms for circuit partitioning

Author keywords

CAD; Circuit partitioning; Genetic algorithms; VLSI design

Indexed keywords

BENCHMARKING; COMPUTER AIDED DESIGN; ENCODING (SYMBOLS); HEURISTIC METHODS; ITERATIVE METHODS; LOGIC DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION; VLSI CIRCUITS;

EID: 6344258307     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (13)

References (19)
  • 1
    • 0024481167 scopus 로고
    • Multiple-way network partitioning
    • Sanchis LA. Multiple-way network partitioning. IEEE Transactions on Computers, Vol.38, No. 1, pp.62-81, 1989.
    • (1989) IEEE Transactions on Computers , vol.38 , Issue.1 , pp. 62-81
    • Sanchis, L.A.1
  • 2
    • 84990479742 scopus 로고
    • An efficient heuristic procedure for partitioning graphs
    • Kernighan BW, Lin S. An Efficient Heuristic Procedure for Partitioning Graphs. Bell System Technical Journal, Vol.49, No.2, pp291-307, 1970.
    • (1970) Bell System Technical Journal , vol.49 , Issue.2 , pp. 291-307
    • Kernighan, B.W.1    Lin, S.2
  • 3
    • 6344246887 scopus 로고    scopus 로고
    • Genetic algorithms for VLSI design
    • Prentice-Hall
    • Pinaki Mazumder. Genetic Algorithms for VLSI Design, Layout & Test Automation. Prentice-Hall, pp41-46, 1999.
    • (1999) Layout & Test Automation , pp. 41-46
    • Mazumder, P.1
  • 6
    • 0021425044 scopus 로고
    • An improved min-cut algorithm for partitioning VLSI networks
    • Krishnamurthy B. An improved min-cut algorithm for partitioning VLSI networks. IEEE Trans on Computer Aided Design., vol.C-33,pp.438-446, 1984.
    • (1984) IEEE Trans on Computer Aided Design , vol.C-33 , pp. 438-446
    • Krishnamurthy, B.1
  • 7
    • 0026191188 scopus 로고
    • Ratio cut partitioning for hierarchical design
    • Wei YC, Cheng CK. Ratio cut partitioning for hierarchical design. IEEE Trans. on CAD, 40(7), pages 911-921, 1991.
    • (1991) IEEE Trans. on CAD , vol.40 , Issue.7 , pp. 911-921
    • Wei, Y.C.1    Cheng, C.K.2
  • 12
    • 0002832195 scopus 로고    scopus 로고
    • A hybrid multilevel/genetic approach for circuit partitioning
    • Alpert CJ, Kahng AB.A hybrid multilevel/genetic approach for circuit partitioning. Physical Design Workshop, pp100-105. 1996
    • (1996) Physical Design Workshop , pp. 100-105
    • Alpert, C.J.1    Kahng, A.B.2
  • 14
    • 4644284990 scopus 로고    scopus 로고
    • The effect of clustering and local search on genetic algorithms
    • Leicester, UK, July
    • Areibi S. The Effect of Clustering and Local Search on Genetic Algorithms, Recent Advances In Soft Computing, Leicester, UK, July 1999.
    • (1999) Recent Advances in Soft Computing
    • Areibi, S.1
  • 16
    • 0032183309 scopus 로고    scopus 로고
    • GEORG: VLSI circuit partitioner with a new genetic algorithm framework
    • Moon BR, Lee YS, Kim CK, GEORG: VLSI Circuit Partitioner with a New Genetic Algorithm Framework. Journal of Intelligent Manufacturing, Vol. 9, pp.401-12, 1998
    • (1998) Journal of Intelligent Manufacturing , vol.9 , pp. 401-412
    • Moon, B.R.1    Lee, Y.S.2    Kim, C.K.3
  • 17
    • 0027148619 scopus 로고
    • Circuit partitioning using a tabu search approach
    • Areibi S, Vannelli A. Circuit Partitioning Using a Tabu Search Approach. ISCAS1993: 1643-1646, 1993.
    • (1993) ISCAS1993 , pp. 1643-1646
    • Areibi, S.1    Vannelli, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.