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Volumn , Issue , 2009, Pages 287-292

Improved-quality real-time stereo vision processor

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; IMAGE CODING; INTEGRATED CIRCUITS; SPECIAL EFFECTS;

EID: 63149117434     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2009.89     Document Type: Conference Paper
Times cited : (11)

References (16)
  • 1
    • 63149131751 scopus 로고    scopus 로고
    • M. Kuhn et al., Efficient ASIC Implementation of a Real-time Depth Mapping Stereo Vision System, Circuits and Systems, Proceedings of the 46th IEEE International Midwest Symposium on 3, 27-30 Dec. 2003 Page(s):1478-1481.
    • M. Kuhn et al., "Efficient ASIC Implementation of a Real-time Depth Mapping Stereo Vision System", Circuits and Systems, Proceedings of the 46th IEEE International Midwest Symposium on Volume 3, 27-30 Dec. 2003 Page(s):1478-1481.
  • 4
    • 29144450031 scopus 로고    scopus 로고
    • FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture
    • Dec, Pages
    • M. Hariyama et al., "FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Volume E88-A, Issue 12, Dec 2005, Page(s):3516-3522.
    • (2005) IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences , vol.E88-A , Issue.12 , pp. 3516-3522
    • Hariyama, M.1
  • 7
    • 4544239289 scopus 로고    scopus 로고
    • A pyramid-based front-end processor for dynamic vision applications
    • July, Pages
    • P.J.Burt, "A pyramid-based front-end processor for dynamic vision applications", Proceedings of the IEEE, July 2002, Volume: 90, Page(s): 1188-1200.
    • (2002) Proceedings of the IEEE , vol.90 , pp. 1188-1200
    • Burt, P.J.1
  • 8
    • 38049026931 scopus 로고    scopus 로고
    • Architecture and Implementation of Real-Time Stereo Vision with Bilateral Background Subtraction
    • Pages
    • Sang-Kyo Han et al., "Architecture and Implementation of Real-Time Stereo Vision with Bilateral Background Subtraction", Lecture Notes in Computer Science, 2007, Volume: 4681, Page(s): 906-912.
    • (2007) Lecture Notes in Computer Science , vol.4681 , pp. 906-912
    • Han, S.-K.1
  • 9
    • 27144468787 scopus 로고    scopus 로고
    • Projective rectification based on relative modification and size extension for stereo image pairs
    • Oct, Pages
    • H.-H.P. Wu et al., "Projective rectification based on relative modification and size extension for stereo image pairs", IEE Proc. Image Signal Processing, Oct 2005, Volume: 152, Page(s):623-633.
    • (2005) IEE Proc. Image Signal Processing , vol.152 , pp. 623-633
    • Wu, H.-H.P.1
  • 12
    • 34250834465 scopus 로고    scopus 로고
    • 1000 frame-sec Stereo Matching VLSI Processor with Adaptive Window-Size Control
    • Pages
    • Masanori Hariyama et al., "1000 frame-sec Stereo Matching VLSI Processor with Adaptive Window-Size Control", Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian, Page(s):123-126.
    • Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian , pp. 123-126
    • Hariyama, M.1
  • 13
    • 4544248891 scopus 로고    scopus 로고
    • VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture
    • Digest of Technical Papers. 2004 Symposium on, Pages
    • Masanori Hariyama et al., "VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture", VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on, Page(s):166-169.
    • (2004) VLSI Circuits , pp. 166-169
    • Hariyama, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.