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Volumn , Issue , 2008, Pages 97-104
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Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain
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Author keywords
[No Author keywords available]
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Indexed keywords
AUTOMOBILE PARTS AND EQUIPMENT;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
MICROCONTROLLERS;
TELECOMMUNICATION SYSTEMS;
AUTOMOTIVE DOMAINS;
BUS SYSTEMS;
FLEXRAY;
GATEWAY SYSTEMS;
HARDWARE MODULES;
KEY COMPONENTS;
NEW APPLICATIONS;
PERFORMANCE COMPARISONS;
RECONFIGURABLE HARDWARES;
ROUTING FUNCTIONALITIES;
ROUTING MECHANISMS;
ROUTING MODULES;
ROUTING TABLES;
SPEED-UP;
TOOL FLOWS;
GATEWAYS (COMPUTER NETWORKS);
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EID: 63049120018
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/FPT.2008.4762371 Document Type: Conference Paper |
Times cited : (8)
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References (10)
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