FPGA-based ultra-low latency HIL fault testing of a permanent magnet motor drive using RT-LAB-XSG

2008 Joint International Conference on Power System Technology POWERCON and IEEE Power India Conference, POWERCON 2008

Volumn , Issue , 2008, Pages

  Dufour, Christian ^a   Bélanger, Jean ^a   Lapointe, Vincent ^a  

^a OPAL RT TECHNOLOGIES   (Canada)

Author keywords

Field programmable gate arrays; Insulated gate bipolar transistors; Permanent magnet machine; Pulse width modulation

Indexed keywords

AC MOTORS; ACTIVE FILTERS; BIPOLAR TRANSISTORS; CONCURRENCY CONTROL; DRIVES; ELECTRIC DRIVES; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC MACHINERY; ELECTRIC POWER TRANSMISSION NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INDUSTRIAL APPLICATIONS; INSULATED GATE BIPOLAR TRANSISTORS (IGBT); LOGIC GATES; MAGNETIC DEVICES; MODULATION; MOTORS; POWER TRANSMISSION; PULSE WIDTH MODULATION; SOFTWARE TESTING; SYNCHRONOUS MOTORS; TRANSIENTS;

CONTROL STRATEGIES; FAULT TESTING; FPGA CHIPS; HARD WARE IN THE LOOPS; IGBT INVERTERS; LOW LATENCIES; MOTOR DRIVES; PERMANENT MAGNET MACHINE; PERMANENT-MAGNET MOTORS; PHASE-DOMAIN MODELS; PMSM DRIVES; PMSM MODELS; REAL-TIME SIMULATIONS; SIMULATION VALIDATIONS; SIMULINK; SINUSOIDAL FLUXES; SOFTWARE PROTECTIONS; TIME STEPS; XILINX SYSTEM GENERATORS;

PERMANENT MAGNETS;

EID: 62949095380     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPST.2008.4745355     Document Type: Conference Paper

References (8)

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