USING CACHE MEMORY TO REDUCE PROCESSOR-MEMORY TRAFFIC

Proceedings - International Symposium on Computer Architecture

Volumn 1998-June, Issue , 1998, Pages 255-262

  Goodman, James R ^a  

^a University of Wisconsin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUS TRAFFIC; CACHE DATA; DATA CONSISTENCY; PERFORMANCE; PROCESS SWITCHES; PROCESSOR MEMORY; SINGLE BOARD COMPUTERS; SINGLE-BOARD COMPUTERS; SPATIAL LOCALITY; TEMPORAL LOCALITY;

CACHE MEMORY;

EID: 62349121522     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/285930.285984     Document Type: Conference Paper

References (27)

1. C. Amdahl, mate communtiution, March 82.
2. J. Bell, D. Casasent, and C. G. Bell, "An innstieation of alternative cache organizations," IE%,'E mms. on Computers, Vol. C-23, No. 4. April 1974, pp. 348-351.
3. C. Beil. J. Judge, J. McNamara. Computer angtnefwtn~: a DEC view of hardware system drsign, Digital Press, Bedford, Mass., 1976.
4. L. M. Censier and P. Feautrier. "A new solution to coherence problems in multicache systems," IEEE pans. on Computers, Vol. C-27, No. 12 December 1976, pp. 1112-1116.
5. M. C. Easton and R. Fagin, "Cold-start vs. warm-start miss ratios," CACM, Vol. 21. No. 10, October 1978. pp. 860-872.
6. H. A. Crosch. "High Speed Arithmetic: the Digital Computer as a Research Tool." Joumol 01 tha Opticcrl Society 01 Arnsricu, Vol. 43. No. 4. (April 1953).
7. C. H. Hoogendoorn. "Reduction of memory interference in multiprocessor systems," Roe. 4th Annual Sgmp. Comput. Arch., 1977, pp. 179163.
8. mar. 741 "System/370 model 155 theory of operation/diagrams manual (volume 5): buffer control unit," IBM System Products Division. Poughkeepsie. N.Y. 1974.
9. "System/370 model 168 theory of operation/diagrams manual (volume l)." Document No. 8122-6931-3, IBM System Products Division. Poughkeepsie. N.Y. 1976.
10. IEEE aoj "proposed microcomputer syste: I∗bus standard (P796 bus)," IEEE Computer Society Subcommtitcs Microcomputer System Bus ckoup, October 1960.
11. K. R. Kaplan and R 0. Winder, "Cache-based computer systems." Computer, March 1973, pp. 30-36.
12. J. R. Knight. "Changes in cznputer performance," Datamation. Vol. 12, No. 9. September 1966, pp. 40-54.
13. "Cache Memory for Microprocessors," Cbmputer Architecture News, ACM - SIGARCH. Vol. 9. No. 5. (August 1961). pp. 6-13.
14. "J. S. Liptay, "Structural aspects of the System/ 360 Model 65. Part II: the cache." IBM Syst. J., Vol. 7, No. 1. 1966, pp. 15-21.
15. R. L.Horton and J. L. Abraham. "Using write back cachi to improve performance of multiuser multiprocessors," 1982 Int. Conf. on Par. Proc., IEEE cat. no. 62CH1794-7, 1962, pp. 326-331.
16. "Analysis of multiprocessor with private cache memories." J. H. Patel. IEEE -pram. on Computers, Vol. C-31, No. 4, April 1962. pp. 296-304.
17. C. S. Rao. "Performance Analysis of Cache Memories," Journcrl of the ACM, Vol.-25 July 1976. pp. 376-395.
18. C. V. Ravishankar and J. Goodman, "Cache implementation for multiple microprocessors." Digest of F'apers. Spr%ng COMPCON 83, IEEE Computer Society Press, March 1963.
19. D. P. Siewiorek. C. G. Bell, and A. Newell. Computer Stnrctures: Principles and Ezamplos, McGraw-Hill, New York, N.Y. 1962.
20. A. J. Smith, "Cache memories," Computig ways, Vol. 14. No. 3. September 1962. pp. 473- 530.
21. J. E. Smith and J. R. Goodman. "A study of instruction cache organizations and replacement policies," Tenth Annuaf Symposium on Computer Architecture, June 1983.
22. M. B. Solomon, Jr., "Economies of Scale and the IBM System/SBO." CACM. Vol. 9, No. 6. June 1966. pp. 435-440.
23. C. K. Tang, "Cache system design in the tightly coupled multiprocessor system." AFIPS Rot., NCC, Vol. 45. pp. 749-753, 1978.
24. Texas instruments YOS Memory Datu Book. Texas Instruments. Inc. Memory Division, Houston, Texas, pp. 106-111. 1962.
25. N. Tredennick. "The IBM micro/370 project," public lecture for Distingukhed Lecturer Stw%es, Computer Sciences Department. University of Wisconsin-Madison, March 31. 1962.
26. L. C. Widdoes. "S-l Multiprocessor architecture (MULT-21." 1979 Annunl Renort - the S-I Project, 'k'olume~l: Architecture, Lawrence Livermore Laboratories, Tech. Report UCID 16619, 1979.
27. s W. C. Yen and K. S. Fu, "Coherence problem in a multicache system," 1982 Int. ConI. on Par. Rot. IEEE cat. no. 62CH1794-7, 1962. pp. 332-339.