Adaptive techniques for leakage power management in l2 cache peripheral circuits

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 563-569

  Homayoun, Houman ^a   Veidenbaum, Alex ^a   Gaudiot, Jean Luc ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE TECHNIQUES; CACHE HIERARCHIES; I/O DRIVERS; L2 CACHES; LEAKAGE CONTROLS; LEAKAGE POWER; LEAKAGE POWER MANAGEMENTS; LEAKAGE POWER REDUCTIONS; MISS RATES; PERIPHERAL CIRCUITS; PROGRAM BEHAVIORS; STATIC TECHNIQUES;

ABERRATIONS; CACHE MEMORY; CONCURRENCY CONTROL; ENERGY MANAGEMENT; RADIOMETERS; SIGNAL FILTERING AND PREDICTION;

LEAKAGE CURRENTS;

EID: 62349111286     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751917     Document Type: Conference Paper

References (27)

1. D. Nicolaescu et al,. Fast Speculative Address Genera-tion and Way Caching for Reducing L1 Data Cache Energy. Proc. IEEE ICCD, 2006.
2. R. Bai et al,. Total leakage optimization strategies for multi-level caches in Proc. ACM Great Lakes symposium on VLSI, 2005.
3. T. Skotnicki et al,.The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits and Devices Magazine, Jan.-Feb. 2005, Vol. 21, Issue: 1.
4. C. H. Kim et al,. A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. on VLSI Systems, vol. 13, 2005, pp. 349-357.
5. S. Borkar et al,. Platform 2015: Intel® Processor and platform evolution for the next decade. Intel Technology Magazine, March 2005.
6. K. Nii, et al. A low power SRAM using auto-backgate-controlled MTCMOS. In ISLPED, 1998, pp. 293-298.
7. M. Bohr. Nanotechnology goals and challenges for electronic applications. IEEE Transactions on Nano- technology, Vol 1, No. 1, March 2002.
8. Y. Takeyama et al,. A Low Leakage SRAM Macro with Replica Cell Biasing Scheme. IEEE Journal Of Solid- State Circuits, Vol. 41, No. 4, April 2006.
9. F. Hamzaoglu et al,. Analysis of Dual-VT SRAM cells with Full-Swing Single-Ended Bit Line Sensing for On-Chip Cache. IEEE Trans. on VLSI Systems, vol. 10, April 2002,
10. D. Marculescu. On the use of microarchitecture-driven dynamic voltage scaling. In Workshop on Complexity-Effective Design, June 2000.
11. SimpleScalar4 tutorial, SimpleScalar LLC. http://www.simplescalar.com/ tutorial.html.
12. K. Nii et al., A 90-nm low-power 32 KByte embedded SRAM with gate leakage suppression circuit for mobile applications, IEEE J. Solid-State Circuits, vol. 39, pp. 684-693, Apr. 2004.
13. M.D. Powell et al,. Gated Vdd: A circuit technique to reduce leakage in deep-submicron cache memories. in Proc. IEEE ISLPED, 2000.
14. A. Agarawal et al., DRG-Cache: A Data Retention Gated-Ground Cache for Low Power, DAC 2002. pp. 473-478.
15. Y. Li et al,. State-preserving vs. non-state-preserving leakage control in caches. in Proc. IEEE DATE, 2004.
16. K. Flautner et al,. Automatic performance setting for dynamic voltage scaling. in Journal of Wireless Networks, pages 260-271, 2001.
17. H. Homayoun and A. V. Veidenbaum,. Reducing Leakage Power in Peripheral Circuit of L2 Caches, IEEE-ICCD 2007.
18. Bharadwaj S. Amrutur et al,. Speed and power scaling of SRAMs, IEEE Journal of Solid State Circuits. Feb 2000, vol. 35.
19. S. Kaxiras et al,. Cache decay: exploiting generational behavior to reduce cache leakage power. IEEE-ISCA, 2001.
20. Pentium M processor on 90 nm process with 2-MB L2 cache. Intel Corp. .Jan. 2005. www.intel.com/design/mobile/datashts/302189.htm.
21. K. Flautner et al,. Drowsy caches: simple techniques for reducing leakage power. IEEE ISCA, 2002.
22. Cacti5, http://quid.hpl.hp.com:9082/cacti/.
23. S. Rusu et al,. A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, JAN 2007.
24. S. Rusu, H. Muljono and B. Cherkauer,. Itanium 2 processor 6M: higher frequency and larger L3 cache. IEEE Micro, Mar-Apr 2004, Volume: 24, Issue: 2.
25. M. Powell et al,. Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. IEEE-ISLPED 2000.
26. B.S. Amrutur, et al., A replica technique for wordline and sense control in low-power SRAM's, IEEE Journal of Solid-State Circuits, vol. 33, No. 8, Aug.2000.
27. J. M. Rabaey et al., Digital integrated circuits: a design perspective, Prentice Hall, Second. Edition, 2003.