Incremental logic synthesis through gate logic structure identification

Proceedings - Design Automation Conference

Volumn , Issue , 1986, Pages 391-397

  Shinsha, T ^a   Kubo, T ^a   Sakataya, Y ^a   Koshishita, J ^a   Ishihara, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER AIDED DESIGN; LOGIC DESIGN; LOGIC SYNTHESIS; MULTIPROCESSING SYSTEMS; STRUCTURE (COMPOSITION);

DESIGN EFFICIENCY; DIGITAL SYSTEM; EDITING SYSTEMS; LARGE COMPUTERS; LOGIC COMPONENTS; LOGIC STRUCTURES; MATRIX METHODS; PHYSICAL DESIGN;

COMPUTER CIRCUITS;

EID: 62349108042     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1986.1586119     Document Type: Conference Paper

References (10)

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2. V. Rajan and D. E. Thomas, "Synthesis by Delayed Binding of Decisions", Proc. of the 22nd DAC, June 1985, pp. 367-373.
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4. O. Karatsu, T. Hoshino, M. Endo and K. Ueda, "An Automatic VLSI Synthesizer", Proc of ISCAS 85, 3une 1985, pp. 403-406.
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6. T. Shinsha, T. Kubo, M. Hikosaka, K. Akiyama and K. Ishihara, "POLARIS: Polarity Propagation Algorithm for Combinational Logic Synthesis", Proc. of the 21th DAC, June 1984, pp. 322-328.
7. T. Shimizu, Y. Takamine, T. Shinsha and T. Kubo, "A Logic Synthesis Algorithm for the Design of a High Performance Processor", Proc. of ISCAS 85, June 1985, pp. 407-410.
8. S. B. Akers, "A Procedure for Functional Design Verification", Proc. of the 10th FTCS, 1980 June, pp. 65-67.
9. G. L. Smith, R. J. Bahnsen and H. Haliiwell, "Boolean Comparison of Hardware and Flowcharts", IBM 3. Res. Develop., Vol. 26, No. 1, 3an. 1982, pp. 106-116.
10. Y. Tsuchiya, M. Morita, Y. Ikariya, S. Uematsu, E. Tsurumi, T. Mori and T. Yanagida, "Establishment of Higher Level Logic Design for Very Large Scale Computer", Proc. of the 23rd DAC, 3une-3uly 1986, this issue.