Celator: A multi-algorithm cryptographic co-processor

Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008

Volumn , Issue , 2008, Pages 438-443

  Fronte, Daniele ^a   Perez, Annie ^b   Payrat, Eric ^c  

^a AIX MARSEILLE UNIVERSITÉ   (France)

^b AIX MARSEILLE UNIVERSITY   (France)

^c Atmel   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COPROCESSOR; DATA PRIVACY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENERAL PURPOSE COMPUTERS; HARDWARE; HASH FUNCTIONS; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; THROUGHPUT;

ADVANCED ENCRYPTION STANDARD; CRYPTOGRAPHIC ALGORITHMS; DATA ENCRYPTION STANDARD; GENERAL PURPOSE PROCESSORS; HARDWARE IMPLEMENTATIONS; PERFORMANCE COMPARISON; RECONFIGURABLE CIRCUITS; SECURE HASH ALGORITHM;

HARDWARE SECURITY;

EID: 62349091083     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReConFig.2008.76     Document Type: Conference Paper

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