A reconfiguration-aware floorplacer for FPGAs

Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008

Volumn , Issue , 2008, Pages 109-114

  Montone, A ^a   Redaelli, F ^a   Santambrogio, M D ^a   Memik, S Ogrenci ^b  

^a POLITECNICO DI MILANO   (Italy)

^b NORTHWESTERN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION INFRASTRUCTURES; FLOOR-PLANNING; FLOORPLAN; FPGA DEVICES; PHYSICAL CONSTRAINTS; RE-CONFIGURABLE ARCHITECTURES; RESOURCE DISTRIBUTIONS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 62349088985     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReConFig.2008.36     Document Type: Conference Paper

References (17)

1. Xilinx Incorporation. ISE 9.2i Manual, 2007.
2. Vaughn Betz and Jonathan Rose. VPR: A new packing, placement and routing tool for FPGA research. Springer-Verlag, London, UK, 1997.
3. J.A. Roy, S.N. Adya, D.A. Papa, and I.L. Markov. Min-cut floorplacement. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 25(7):1313-1326, July 2006.
4. S.N. Adya, S. Chaturvedi, J.A. Roy, D.A. Papa, and I.L. Markov. Unification of partitioning, placement and floorplanning. Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, pages 550-557, Nov. 2004.
5. Yan Feng and Dinesh P. Mehta. Heterogeneous floorplanning for fpgas. vlsid, 0:257-262, 2006.
6. Xilinx Inc. Virtex II - Family Overview, Dec 2007.
7. S.N. Adya and I.L. Markov. Fixed-outline floorplanning: enabling hierarchical design. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 11(6):1120-1135, Dec. 2003.
8. Kiarash Bazargan, Ryan Kastner, and Majid Sarrafzadeh. 3-d floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems, rsp, 00:38, 1999.
9. Milan Vasilko. Dynasty: A temporal floorplanning based cad framework for dynamically reconfigurable logic systems. In FPL '99: Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications, pages 124-133, London, UK, 1999. Springer-Verlag.
10. Ping-Hung Yuh, Chia-Lin Yang, and Yao-Wen Chang. Temporal floor-planning using the t-tree formulation. Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, pages 300-305, Nov. 2004.
11. Ping-Hung Yuh, Chia-Lin Yang, and Yao-Wen Chang. Temporal floorplanning using the three-dimensional transitive closure subgraph. ACM Trans. Des. Autom. Electron. Syst., 12(4):37, 2007.
12. L. Singhal and E. Bozorgzadeh. Multi-layer floorplanning on a sequence of reconfigurable designs. Field Programmable Logic and Applications, 2006. FPL '06. International Conference on, pages 1-8, Aug. 2006.
13. H. Murata, K. Fujiyoshi, S. Nakatake, and Y Kajitani. Vlsi module placement based on rectangle-packing by the sequence-pair. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 15(12):1518-1524, Dec 1996.
14. Xilinx Incorporation. Virtex 5 - Family Overview, Dec 2007.
15. Xilinx Incorporation. Early Access Partial Reconfiguration User Guide, 2006.
16. S. Corbetta, F. Ferrandi, M. Morandi, M. Novati, M.D. Santambrogio, and D. Sciuto. Two novel approaches to online partial bitstream relocation in a dynamically reconfigurable system. isvlsi, 00:457-458, 2007.
17. H. Kalte, G. Lee, M. Porrmann, and U. Ruckert. Replica: A bitstream manipulation filter for module relocation in partial reconfigurable systems, ipdps, 04:151b, 2005.