High multiplication factor capacitor multiplier for an on-chip PLL loop filter

Electronics Letters

Volumn 45, Issue 5, 2009, Pages 239-240

  Choi, J ^a   Park, J ^a   Kim, W ^a   Lim, K ^a   Laskar, J ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; PHASE LOCKED LOOPS;

CAPACITOR MULTIPLIERS; CMOS TECHNOLOGIES; CURRENT CONSUMPTION; INTEGER-N; LOOP FILTERS; LOW-POWER CONSUMPTION; MULTIPLICATION FACTORS; ON CHIPS; ON-CHIP CAPACITORS; SMALL CHIP AREAS;

CAPACITANCE;

EID: 61349169647     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20092874     Document Type: Article

References (5)

1. Tang, Y., Ismail, M., and Bibyk, S.: ' Adaptive Miller capacitor multiplier for compact on-chip PLL filter ', Electron. Lett., 2003, 39, (1), p. 43-45 0013-5194
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3. Shu, K., Sanchez-Sinencio, E., Silva-Martinez, J., and Embabi, S.: ' A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier ', IEEE J. Solid-State Circuits, 2003, 38, (6), p. 866-874 0018-9200
4. Hwang, I.: ' Area-efficient and self-biased capacitor multiplier for on-chip loop filter ', Electron. Lett., 2006, 42, (24), p. 1392-1393 0013-5194
5. Choi, J., Lim, K., and Laskar, J.: ' A ring VCO with wide and linear tuning characteristics for a cognitive radio system ', Radio Frequency Integrated Circuits Symp., Atlanta, GA, USA, 2008, p. 395-398