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Volumn 2, Issue , 2005, Pages 557-563

Reducing communication time through message prefetching

Author keywords

Latency reduction; Message prefetching; MPI; Page protection; Page version

Indexed keywords

COMMUNICATION TIME; EXECUTION SPEED; LATENCY REDUCTION; MESSAGE LATENCY; MESSAGE RECEIVERS; MPI APPLICATIONS; PARALLEL APPLICATION; POOR PERFORMANCE; PREFETCHES; PREFETCHING; PREFETCHING TECHNIQUES; RUN-TIME LIBRARY;

EID: 60749116009     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (18)
  • 3
    • 77949556549 scopus 로고    scopus 로고
    • http://www.tc.cornell.edu/
  • 9
    • 35248859849 scopus 로고    scopus 로고
    • Improving the Performance of Collective Operations in MPICH
    • September
    • R. Thakur and W. Gropp, "Improving the Performance of Collective Operations in MPICH," European PVM/MPI Users' Group Conference, September 2003, pp. 257-267.
    • (2003) European PVM/MPI Users' Group Conference , pp. 257-267
    • Thakur, R.1    Gropp, W.2
  • 12
    • 0003605996 scopus 로고
    • The NAS Parallel Benchmarks 2.0,
    • Technical Report NAS-95-020, NASA Ames Research Center
    • D. Bailey, T. Harris, W. Saphir, R. v.d. Wijngaart, A. Woo, and M. Yarrow, "The NAS Parallel Benchmarks 2.0," Technical Report NAS-95-020, NASA Ames Research Center, 1995.
    • (1995)
    • Bailey, D.1    Harris, T.2    Saphir, W.3    Wijngaart, R.V.D.4    Woo, A.5    Yarrow, M.6
  • 13
    • 1342295420 scopus 로고    scopus 로고
    • The use of the MPI communication library in the NAS Parallel Benchmark,
    • Technical Report CSE-TR-386-99, Department of Computer Science, University of Michigan
    • T. Tabe and Q. F. Stout, "The use of the MPI communication library in the NAS Parallel Benchmark," Technical Report CSE-TR-386-99, Department of Computer Science, University of Michigan, 1999.
    • (1999)
    • Tabe, T.1    Stout, Q.F.2
  • 14
    • 0018106484 scopus 로고
    • Sequential Program Prefetching in Memory Hierarchies
    • December
    • A. J. Smith, "Sequential Program Prefetching in Memory Hierarchies", IEEE Computer, December 1978, pp. 7-21.
    • (1978) IEEE Computer , pp. 7-21
    • Smith, A.J.1
  • 16
    • 0031988272 scopus 로고    scopus 로고
    • Tolerating Latency in Multi-processors through Compiler-Inserted Prefetching
    • February
    • T. C. Mowry, "Tolerating Latency in Multi-processors through Compiler-Inserted Prefetching", ACM Transactions on Computer Systems, Vol. 16, No. 1, February 1998, pp. 55-92.
    • (1998) ACM Transactions on Computer Systems , vol.16 , Issue.1 , pp. 55-92
    • Mowry, T.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.