Air spacer MOSFET technology for 20nm node and beyond

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn , Issue , 2008, Pages 53-56

  Park, Jemin ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AIR SPACERS; CMOS INVERTERS; GATE TRANSISTORS; MIXED-MODE SIMULATIONS; MOS FETS; POWER CONSUMPTION; SELF ALIGNED CONTACTS; SPACER TECHNOLOGIES; SWITCHING ENERGIES; TCAD SIMULATIONS;

INTEGRATED CIRCUITS; NITRIDES; TECHNOLOGY;

MOSFET DEVICES;

EID: 60649115718     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2008.4734461     Document Type: Conference Paper

References (4)

1. M.togo, et al., "A Gate-side Air-gap Structure(GAS) to Reduce the Parasitic Capacitance in MOSFETs", Symposium on VLSI tech. Dig., p.38, 1996.
2. Chunshan Yin, et al, "An Air Spacer Technology for Improving Short-Channel Immunity of MOSFETs With Raised Source/Drain and High-k Gate Dielectric", Electron Device Letter, vol.26(5), p. 323, 2005
3. TSUPREM4 User Manual, Synopsys, Mountain View, CA.
4. SENTAURUS User Manual, Synopsys, Mountain View, CA.