A novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn , Issue , 2008, Pages 1146-1149

  Pei, Chengwen ^a   Booth, Roger ^a   Ho, Herbert ^a   Kusaba, Naoyoshi ^a   Li, Xi ^a   Brodsky, MaryJane ^a   Parries, Paul ^a   Shang, Huiling ^a   Divakaruni, Rama ^a   Iyer, Subramanian ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA SAVINGS; BULK CMOS; CHIP LEVELS; DECOUPLING CAPACITORS; DEEP TRENCHES; EMBEDDED DRAMS; GATE OXIDES; LOW-POWER; PROCESS CYCLES; PROCESS SIMPLIFICATIONS; REAL ESTATES; REDUCED COSTS;

CAPACITORS; ELECTRIC CONVERTERS; GATES (TRANSISTOR); INTEGRATED CIRCUITS;

CAPACITANCE;

EID: 60649093971     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2008.4734752     Document Type: Conference Paper

References (6)

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2. G. Wang et al, "A 0.127um2 High Performance 65nm SOI Based Embedded DRAM for on-Processor Applications." IEDM' 06
3. T. Kirihata et al., "An 800MHz Embedded DRAM with a Concurrent Refresh Mode." ISSCC'04
4. R. Matick and S. Chuster, "Logic-based eDRAM: Origins and Rationale foruse,"IBM JRD, Jan. '05
5. S. Iyer et al, "Embedded DRAM: Technology Platform for the BlueGene/L Chip,"IBM JRD, March-May '05
6. S. Iyer and H. Kalter, "Embedded DRAM Technology: Opportunities and Challenges,"IEEE Spectrum, 4/99