Scaling study of nanowire and multi-gate MOSFETs

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn , Issue , 2008, Pages 57-60

  Chen, Chin Yu ^a   Liao, Yi Bo ^a   Chiang, Meng Hsueh ^a  

^a NATIONAL ILAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

45NM NODES; CAPACITIVE COUPLINGS; DEVICE PERFORMANCE; DIMENSION CONSTRAINTS; MOSFETS; N-MOSFETS; NANOWIRE DEVICES; ON BODIES; SCALING CAPABILITIES; SCALING STUDIES; SHORT-CHANNEL EFFECTS; SURROUNDING GATES; THREE-DIMENSIONAL NUMERICAL SIMULATIONS;

FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; THREE DIMENSIONAL;

NANOWIRES;

EID: 60649088932     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2008.4734462     Document Type: Conference Paper

References (10)

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