Mapping packet processing applications on a systolic Array network processor

2008 International Conference on High Performance Switching and Routing, HPSR 2008

Volumn , Issue , 2008, Pages 213-220

  Morandi, Olivier ^a   Risso, Fulvio ^a   Rolando, Pierluigi ^a   Hagsand, Olof ^b   Ekdahl, Peter ^c  

^a POLITECNICO DI TORINO   (Italy)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^c Xelerated AB   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CIRCUIT THEORY; PACKET NETWORKS; PACKET SWITCHING; PROGRAM COMPILERS; SOFTWARE ENGINEERING;

AGGREGATE THROUGHPUTS; HARDWARE PLATFORMS; HARDWARE RESOURCES; LOW LEVELS; NETWORK PROCESSORS; PACKET PROCESSING; PIPELINED ARCHITECTURES; SOFTWARE DEVELOPMENT TOOLS; SOFTWARE ENGINEERS; THROUGHPUT PERFORMANCE; VIRTUAL MACHINES; WORST-CASE PERFORMANCE; XELERATED;

HIGH LEVEL LANGUAGES;

EID: 60649088291     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HSPR.2008.4734446     Document Type: Conference Paper

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