Non-destructive inverse modeling of copper interconnect structure for 90nm technology node

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn 2003-January, Issue , 2003, Pages 31-34

  Kunikiyo, T ^a   Watanabe, T ^a   Kanamoto, T ^a   Asazato, H ^b   Shirota, M ^a   Eikyu, K ^a   Ajioka, Y ^a   Makino, H ^a   Ishikawa, K ^a   Iwade, S ^c   Inoue, Y ^a   Yamashita, K ^d   Kobayashi, M ^d   Gohda, A ^d   Oda, Y ^d   Yamaguchi, R ^d   Umimoto, H ^d   Ohtani, K ^d  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Design   (Japan)

^c OSAKA INSTITUTE OF TECHNOLOGY   (Japan)

^d PANASONIC CORPORATION   (Japan)

Author keywords

Capacitance measurement; Copper; Current measurement; Dielectric measurements; Feedback; Inverse problems; Parameter extraction; Parasitic capacitance; Process control; Testing

Indexed keywords

CAPACITANCE; CAPACITANCE MEASUREMENT; COPPER; ELECTRIC CURRENT MEASUREMENT; EXTRACTION; FEEDBACK; INTEGRATED CIRCUIT INTERCONNECTS; PARAMETER EXTRACTION; PROCESS CONTROL; SEMICONDUCTOR DEVICES; TESTING;

90 NM TECHNOLOGY NODE; CAPACITANCE VARIATION; CHARGE-BASED CAPACITANCE MEASUREMENTS; CROSS-SECTIONAL STRUCTURES; DIELECTRIC MEASUREMENTS; INTER-LAYER DIELECTRICS; PARAMETERS EXTRACTION; PARASITIC CAPACITANCE;

INVERSE PROBLEMS;

EID: 60649083648     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2003.1233630     Document Type: Conference Paper

References (3)

1. J. C. Chen et al., Tech. Dig. of IEDM, 1996, pp.69-72.
2. International Technology Roadmap for Semiconductors, SIA, 2002.
3. G. E. P. Box and N. R. Draper, Empirical model-building and response surfaces, John Wiley and Sons, New York, 1987.