High performance AES design using pipelining structure over GF((2 4) 2)

ICSPC 2007 Proceedings - 2007 IEEE International Conference on Signal Processing and Communications

Volumn , Issue , 2007, Pages 716-719

  Abdel hafeez, Saleh ^a   Sawalmeh, Ahmed ^b   Bataineh, Sameer ^a  

^a JORDAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Jordan)

^b Technical and Vocational Training Corporation TVTC   (Saudi Arabia)

Author keywords

AES pipeline; FPGA; GF((2 4) 2); Rijndael; S box

Indexed keywords

AES PIPELINE; FPGA; GF((2 4) 2); RIJNDAEL; S-BOX;

CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PARALLEL ALGORITHMS; SIGNAL PROCESSING;

PIPELINES;

EID: 60349086477     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSPC.2007.4728419     Document Type: Conference Paper

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