Determining the optimal probing lot size for the wafer probe operation in semiconductor manufacturing

European Journal of Operational Research

Volumn 197, Issue 1, 2009, Pages 126-133

  Wang, Chih Hsiung ^a  

^a NATIONAL PINGTUNG UNIVERSITY   (Taiwan)

Author keywords

Deteriorating process; Lot size; Wafer probing operation

Indexed keywords

DETERIORATION; ELECTRIC CONDUCTIVITY; OPTIMIZATION; PERMANENT MAGNETS; PROBES; SEMICONDUCTING INDIUM; SEMICONDUCTOR MATERIALS;

DETERIORATING PROCESS; FAILURE RATES; GEOMETRIC SHIFTS; INCREASING FAILURE RATES; INSPECTION ERRORS; LOT SIZE; MINIMAL REPAIRS; NUMERICAL EXAMPLES; OPTIMAL LOT SIZES; PROCESSING TIME; SEMICONDUCTOR MANUFACTURING; UPPER BOUNDS; WAFER PROBES; WAFER PROBING OPERATION; WEIBULL;

WEIBULL DISTRIBUTION;

EID: 59649108525     PISSN: 03772217     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.ejor.2008.05.031     Document Type: Article

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