Hiding latency through bulk transfer and prefetching in distributed shared memory multiprocessors

Proceedings - 4th International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, HPC-Asia 2000

Volumn 1, Issue , 2000, Pages 164-166

  Roh, Yangwoo ^a   Seong, Byeong Hag ^a   Park, Daeyeon ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED COMPUTER SYSTEMS;

DISTRIBUTED SHARED MEMORY; DISTRIBUTED SHARED MEMORY MULTIPROCESSORS; LATENCY HIDING; PREFETCH SCHEDULING; REDUCED LATENCIES; REMOTE ACCESS; REPLICATED DATA; SHARED MEMORY PARADIGM;

MEMORY ARCHITECTURE;

EID: 59449095231     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPC.2000.846540     Document Type: Conference Paper

References (4)

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2. T. Mowry, M. S. Lam, and A. Gupta. Design and Evaluation of a compiler algorithm for prefetching. In Proceedings of the 5th Int'l Conf. on Architectural Support for Programming Language and Operating Systems, pages 62-73, 1992.
3. D. Park and R. H. Saavedra. Adaptive Granularity : Transparent integration of fine- and coarse-grain communication. In Proceedings of PACT, pages 260-268, 1996.
4. D. Park and R. H. Saavedra. Trojan: A high-performance simulator for shared memory architectures. In Proceedings of SIMULATION, pages 44-53, 1996.