Comparative evaluation of memory models for chip multiprocessors

Transactions on Architecture and Code Optimization

Volumn 5, Issue 3, 2008, Pages

  Leverich, Jacob ^a   Arakida, Hideho ^a   Solomatnikov, Alex ^a   Firoozshahian, Amin ^a   Horowitz, Mark ^a   Kozyrakis, Christos ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Cache coherence; Chip multiprocessors; Locality optimizations; Parallel programming; Streaming memory

Indexed keywords

BANDWIDTH OPTIMIZATIONS; BANDWIDTH REQUIREMENTS; BEST EFFORTS; CACHE COHERENCE; CHIP MULTIPROCESSORS; COMPARATIVE EVALUATIONS; COMPETING MODELS; COMPUTATIONAL CAPABILITIES; DATA PARALLELS; DATA RE USE; ENERGY CONSUMPTION; IN BUILDINGS; LATENCY TOLERANCES; LOCALITY OPTIMIZATIONS; MEMORY MODELS; ON-CHIP MEMORIES; PRE-FETCHING; PROGRAMMING MODELS; STREAM PROGRAMMING; STREAMING MEMORY; STREAMING MODELS;

APPLICATIONS; BANDWIDTH; CODES (SYMBOLS); COHERENT LIGHT; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SOFTWARE REUSABILITY; IMAGE CODING; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARALLEL PROGRAMMING; PROGRAMMING THEORY; SYSTEMS ANALYSIS; TELECOMMUNICATION SYSTEMS;

CACHE MEMORY;

EID: 59449085862     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1455650.1455651     Document Type: Article

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