Analysis of the influence of substrate on the performance of on-chip MOS decoupling capacitors

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 2, 2009, Pages 484-494

  Rius, Josep ^a   Meijer, Maurice ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Distributed parameter circuit; On chip decoupling capacitor; Wafer substrate

Indexed keywords

CAPACITANCE; CAPACITORS; DIELECTRIC DEVICES; ELECTRIC CONVERTERS; MOS CAPACITORS; MOS DEVICES;

CLOSED-FORM EXPRESSIONS; DECOUPLING CAPACITORS; DESIGN OPTIMIZATIONS; DISTRIBUTED PARAMETER CIRCUIT; FIGURE OF MERITS; FREQUENCY RANGES; HIGH-FREQUENCY POWER; ON CHIPS; ON-CHIP DECOUPLING CAPACITOR; PERFORMANCE QUALIFICATIONS; SIMULATIONS AND MEASUREMENTS; WAFER SUBSTRATE;

SUBSTRATES;

EID: 59349109826     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2010806     Document Type: Article

References (13)

1. International Technology Roadmap for Semiconductors, Assembly and Packaging, ITRS, 2005.
2. M. Popovich, A. V. Mezhiba, and E. G. Friedman, Power Distribution Networks with on-Chip Decoupling Capacitors. New York: Springer, 2008.
3. A. Hastings, The Art of Analog Layout. Upper Saddle River, NJ: Prentice Hall, 2001.
4. T. H. Lee, The Design of CMOS Radio-Frequency Integmted Circuits, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 2004.
5. R. Aparicio and A. Hajimiri, "Capacity limits and matching properties of integrated capacitors," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 384-393, Mar. 2002.
6. N. Inoue, H. Ohtake, N. Furutake, T. Onodera, S. Saito, A. Tanabe, M. Tagami, M. Tada, and Y. Hayashi, "High performance high-k MIM capacitor with plug-in-plate (PiP) for power delivery line of high-speed MPUs," in Proc. IEEE Int. Interconnect Technology Conf., Jun. 2006, pp. 63-65.
7. P. Larsson, "Parasitic resistance in a MOS transistor used as on-chip decoupling capacitance," IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 574-576, Apr. 1997.
8. X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M. Jamal Deen, P. R. Gray, and Ch. Hu, "An effective gate resistance model for CMOS RF and noise modeling," in Proc. Int. Electron Devices Meeting (IEDM), 1998, pp. 961-964.
9. J. Rius and M. Meijer, "A high-frequency nonquasi-static analytical model including gate leakage effects for on-chip decoupling capacitors," IEEE Trans. Adv. Packag., vol. 29, pp. 88-97, Feb. 2006.
10. Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: McGraw-Hill, 1999.
11. H. Lan, T. W. Chen, Ch. O. Sui, P. Nikaeen, J. W. Kim, and R. W. Dutton, "Synthesized compact models and experimental verifications for substrate noise coupling in mixed-signal ICs," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1817-1829, Aug. 2006.
12. A. J. Scholten, L. F. Tiemeijer, P. W. H. de Vreede, and D. B. M. Klaassen, "A large signal non-quasi-static MOS model for RF circuit simulation," in Proc. Int. Electron Devices Meeting (IEDM), Dec. 1999, pp. 163-166.
13. M. S. Ghausi and J. Kelly, Introduction to Distributed-Parameter Networks. New York: Holt, Rinehart and Winston, 1968.