A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 833-836

  Nishikawa, Yukinari ^a   Kawahito, Shoji ^a   Furuta, Masanori ^a   Tamura, Toshihiro ^b  

^a SHIZUOKA UNIVERSITY   (Japan)

^b Chiyodafujimi Bldg   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COSINE TRANSFORMS; DIGITAL CAMERAS; IMAGE COMPRESSION; IMAGE SENSORS; INTEGRATED CIRCUITS; PIXELS;

CMOS IMAGE SENSOR; CMOS TECHNOLOGY; HIGH-SPEED IMAGE SENSORS; IMAGE COMPRESSION CIRCUIT; IMAGE ENCODING; NOISE CANCELING; PARALLEL IMAGE COMPRESSION; PROCESSING ELEMENTS;

IMAGE PROCESSING;

EID: 59249094051     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405857     Document Type: Conference Paper

References (9)

1. M. Furuta, T. Inoue, Y. Nishikawa, S. Kawahito, A 3500fps High-Speed CMOS Image Sensor with 12b Column-Parallel Cyclic A/D Converters , Proc. VLSI Circuits Symp. , pp. 27-28, Jun. 2006.
2. A. Krymski, D. Van Blerkom, A. Andersson, N. Bock, B. Mansoorian and E. R. Fossum, . A High Speed, 500 Frame/s, 1024-1024 CMOS Active Pixel Sensor, . in Proc. IEEE VLSI Circuit Symp. , pp. 137-138, Jun. 1999.
3. A. I. Krymski and N. Tu, . A 9-V/Lux-s 5000-Frames/s 512-512 CMOS Sensor, . IEEE Trans. Electron Devices, vol. 50, no. 1, pp. 136-143, Jan. 2003.
4. A. Krymski, K. Tajima, . CMOS Image Sensor with integrated 4Gb/s Camera Link Transmitter, . Dig. Tech. Papers, IEEE Int. Solid-State Circuits Conf. , pp. 504-505, Feb. 2006.
5. K. Aizawa et al, . Computational image sensor for on sensor compression, . IEEE Trans. on Electron Devices, vol. 44 No. 10 pp. 1724-1730. 1997.
6. Shoji Kawahito, et al, . A CMOS Image Sensor with Analog Two-Dimensional DCT-Based Compression Circuits for One-Chip Cameras. . IEEE J. Solid-state circuits, vol. 32, no. 12, Dec. 1997.
7. M. Furuta, S. Kawahito, T. Inoue, Y. Nishikawa, . A cyclic A/D converter with pixel noise and column-wise offset cancellation for CMOS image sensors, . 7H1, Proc. European Solid-State Circuits Conf. pp. 411-414, Sep. 2005.
8. Shin-ichi Uramoto, et al, . A 100-MHz 2-D Discrete Cosine Transform Core Processor, . IEEE J. Solid-state circuits, vol. 27, no. 4, pp. 492-499, Apr. 1992.
9. http://www. roper. co. jp/redlake/x4. html