AES hardware implementation in FPGA for algorithm acceleration purpose

ICSES'08 - ICSES 2008 International Conference on Signals and Electronic Systems, Proceedings

Volumn , Issue , 2008, Pages 137-140

  Gielata, Artur ^a   Russek, Pawel ^a   Wiatr, Kazimierz ^a  

^a AGH UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Poland)

Author keywords

AES; Cryptography; FPGA; Hardware acceleration

Indexed keywords

CRYPTOGRAPHY; ELECTRONICS ENGINEERING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FIGHTER AIRCRAFT; PIPELINES;

AES; CIPHER PROCESSES; CRYPTOGRAPHIC ALGORITHMS; FPGA; HARDWARE ACCELERATION; HARDWARE IMPLEMENTATIONS; MAXIMUM SPEEDS; NETWORK APPLICATIONS; PIPELINE ARCHITECTURES; RECONFIGURABLE HARDWARES; RIJNDAEL ALGORITHMS; SPEED-UP; SYNTHESIS OF; VIRTEX4;

HARDWARE;

EID: 58149287865     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSES.2008.4673377     Document Type: Conference Paper

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