A Sub-2 W low power IA processor for mobile internet devices in 45 nm high-k metal gate CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 73-82

  Gerosa, Gianfranco ^a   Curtis, Steve ^a   D'Addeo, Michael ^a   Jiang, Bo ^a   Kuttanna, Belliappa ^a   Merchant, Feroze ^a   Patel, Binta ^a   Taufique, Mohammed H ^a   Samarchi, Haytham ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Low power Intel Architecture processor; Mobile internet devices

Indexed keywords

CACHE MEMORY; DECODING; DESIGN; INTERNET; MICROPROCESSOR CHIPS; MOBILE DEVICES; PIPELINES; TRANSISTORS;

AVERAGE POWERS; CMOS PROCESSES; DIE SIZES; DUAL MODES; EXECUTION UNITS; FLOATING POINTS; FRONT ENDS; INSTRUCTIONS PER CYCLES; L2 CACHES; LOW LEAKAGES; LOW POWER INTEL ARCHITECTURE PROCESSOR; METAL GATES; MOBILE INTERNET DEVICES; MOBILE PCS;

COMPUTER ARCHITECTURE;

EID: 58149242627     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2007170     Document Type: Conference Paper

References (6)

1. G. Gerosa et al., "A sub 1 W to 2 W low power IA processor for mobile internet devices and ultra-mobile PCs in 45 nm high-k metal gate CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 256-257.
2. K. Mistry et al., "A 45 nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging," in Tech. Dig. IEDM, Dec. 2007.
3. V. George et al., "PENRYN: 45-nm next generation Intel Core 2 processor," in Proc. ASSCC, Nov. 2007.
4. F. Hamzaoglu et al., "A 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 376-377.
5. B. Kuttanna, "Inside the Intel ATOM processor," in Proc. Microprocessor Forum 2008 Japan, Jul. 17, 2008.
6. T. R. Halfhill, "Intel's tiny ATOM," Intel Corp., Microprocessor Report, Apr. 7, 2008.