Characteristic features of 1-D ballistic transport in nanowire MOSFETs

IEEE Transactions on Nanotechnology

Volumn 7, Issue 6, 2008, Pages 787-794

  Kim, Raseong ^a   Lundstrom, Mark S ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Ballistic transport; MOSFETs; Nanowire (NW) transistor; Quantum wires; Semiconductor device modeling

Indexed keywords

DRAIN CURRENT; ELECTRIC CONDUCTIVITY; MOSFET DEVICES; NANOWIRES; QUANTUM CHEMISTRY; QUANTUM ELECTRONICS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR MATERIALS; SEMICONDUCTOR QUANTUM WIRES; SEMICONDUCTOR SWITCHES; TRANSISTORS; TRANSPORT PROPERTIES; WIRE;

ANALYTIC MODELS; BALLISTIC MODELS; BALLISTIC TRANSPORT; CURRENT INCREASES; DEVICE PARAMETERS; DEVICE PERFORMANCES; DRAIN VOLTAGES; GATE VOLTAGES; MOSFETS; QUANTUM FEATURES; QUANTUM WIRES; SEMICONDUCTOR DEVICE MODELING; SUB BANDS; TEMPERATURE PERFORMANCES;

BALLISTICS;

EID: 58149215952     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2008.920196     Document Type: Article

References (23)

1. H.-S. P. Wong, K. K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel," in IEDM Tech. Dig., Washington, DC, Dec. 1997, pp. 427-430.
2. S. J. Tans, A. R. M. Verschueren, and C. Dekker, "Room-temperature transistor based on a single carbon nanotube," Nature, vol. 393, pp. 49-52, May 1998.
3. J. Xiang, W Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, "Ge/Si nanowire heterostructures as high-performance field-effect transistors," Nature, vol. 441, pp. 489-493, May 2006.
4. N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S. R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channelorientation and low temperature on device performance," in IEDM Tech. Dig., San Francisco, CA, Dec. 2006, pp. 547-550.
5. K. H. Yeo, S. D. Suk, M. Li, Y.-Y. Yeoh, K. H. Cho, K.-H. Hong, S. Yun, M. S. Lee, N. Cho, K. Lee, D. Hwang, B. Park, D.-W. Kim, D. Park, and B.-I. Ryu, "Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires," in IEDM Tech. Dig., San Francisco, CA, Dec. 2006, pp. 539-542.
6. K. H. Cho, S. D. Suk, Y. Y. Yeoh, M. Li, K. H. Yeo, D.-W. Kim, S. W. Hwang, D. Park, and B.-I. Ryu, "Observation of single electron tunneling and ballistic transport in twin silicon nanowire MOSFETs (TSNWFETs) fabricated by top-down CMOS process," in IEDM Tech. Dig., San Francisco, CA, Dec. 2006, pp. 543-546.
7. J.-P. Colinge, A. J. Quinn, L. Floyd, G. Redmond, J. C. Alderman, W Xiong, C. R. Cleavelin, T. Schulz, K. Schruefer, G. Knoblinger, and P. Patruno, "Low-temperature electron mobility in trigate SOI MOSFETs," IEEE Electron Device Lett., vol. 27, no. 2, pp. 120-122, Feb. 2006.
8. K. Morimoto, Y. Hirai, K. Yuki, and K. Morita, "Fabrication and transport properties of silicon quantum wire gate-all-around transistor," Jpn. J. Appl. Phys., vol. 35, pp. 853-857, Feb. 1996.
9. M. Je, S. Han, I. Kim, and H. Shin, "A silicon quantum wire transistor with one-dimensional subband effects," Solid-State Electron., vol. 44, pp. 2207-2212, Dec. 2000.
10. J. P. Colinge, W Xiong, C. R. Cleavelin, T. Schulz, K. Schrufer, K. Matthews, and P. Patruno, "Room-temperature low-dimensional effects in pi-gate SOI MOSFETs," IEEE Electron Device Lett., vol. 27, no. 9, pp. 775-777, Sep. 2006.
11. A. Rahman, J. Guo, S. Datta, and M. S. Lundstrom, "Theory of ballistic nanotransistors," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1853-1864, Sep. 2003.
12. M. Lundstrom and J. Guo, Nanoscale Transistors: Device Physics, Modeling and Simulation. New York: Springer-Verlag, 2006.
13. K. Natori, Y. Kimura, and T. Shimizu, "Characteristics of a carbon nanotube field-effect transistor analyzed as a ballistic nanowire fieldeffect transistor," J. Appl. Phys., vol. 97, pp. 034306-1-034306-7, Feb. 2005.
14. J. S. Blakemore, "Approximations for Fermi-Dirac integrals, especially the function F-1/2 (η) used to describe electron density in a semiconductor," Solid-State Electron., vol. 25, pp. 1067-1076, Nov. 1982.
15. A. Rahman, M. S. Lundstrom, and A. W Ghosh, "Generalized effectivemass approach for n-type metal-oxide-semiconductor field-effect transistors on arbitrarily oriented wafers," J. Appl. Phys., vol. 97, pp. 053702-1-053702-12, Mar. 2005.
16. G. Klimeck, F. Oyafuso, T. B. Boykin, R. C. Bowen, and P. von Allmen, "Development of a nanoelectronic 3-D (NEMO 3-D) simulator for multimillion atom simulations and its application to alloyed quantum dots," CMES, vol. 3, pp. 601-642, 2002.
17. P. F. Bagwell and T. P. Orlando, "Landauer's conductance formula and its generalization to finite voltages," Phys. Rev. B, vol. 40, pp. 1456-1464, Jul. 1989.
18. G. Liang, J. Xiang, N. Kharche, G. Klimeck, C. M. Lieber, and M. Lundstrom, "Performance analysis of a Ge/Si core/shell nanowire field-effect transistor," Nano Lett., vol. 7, pp. 642-646, Mar. 2007.
19. A. Hazeghi, T. Krishnamohan, and H.-S. P. Wong, "Schottky-barrier carbon nanotube field-effect transistor modeling," IEEE Trans. Electron Devices, vol. 54, no. 3, pp. 439-445, Mar. 2007.
20. O. Hayden, M. T. Bjork, H. Schmid, H. Riel, U. Drechsler, S. F. Karg, E. Lortscher, and W Riess, "Fully depleted nanowire field-effect transistor in inversion mode," Small, vol. 3, pp. 230-234, Feb. 2007.
21. N. Neophytou, A. Paul, M. S. Lundstrom, and G. Klimeck, "Selfconsistent simulations of nanowire transistors using atomistic basis sets," in Proc. SISPAD, Vienna, Austria, Sep. 2007, pp. 217-220.
22. S. Hani, L. A. K. Donev, M. Kindermann, and P. L. McEuen, "Measurement of the quantum capacitance of interacting electrons in carbon nanotubes," Nat. Phys., vol. 2, pp. 687-691, Oct. 2006.
23. R. Tu, L. Zhang, Y. Nishi, and H. Dai, "Measuring the capacitance of individual semiconductor nanowires for carrier mobility assessment," Nano Lett., vol. 7, pp. 1561-1565, Jun. 2007.